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SN54LVTH182646AHV

更新时间： 2024-11-19 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路测试信息通信管理
页数 文件大小 规格书
36页 550K
描述
3.3-V ABT SCAN TEST DEVICES WITH 18-BIT TRANSCEIVERS AND REGISTERS

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SN54LVTH182646AHV 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFF, QFL68,.5SQ,25针数：68
Reach Compliance Code：unknown风险等级：5.84
其他特性：DIRECTION CONTROL控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：LVT
JESD-30 代码：S-GQFP-F68长度：12.51 mm
逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER最大I（ol）：0.048 A
位数：9功能数量：2
端口数量：2端子数量：68
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：QFF
封装等效代码：QFL68,.5SQ,25封装形状：SQUARE
封装形式：FLATPACK电源：3.3 V
最大电源电流（ICC）：35 mAProp。Delay @ Nom-Sup：5.9 ns
传播延迟（tpd）：8.7 ns认证状态：Not Qualified
座面最大高度：3.86 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：QUAD翻译：N/A
触发器类型：POSITIVE EDGE宽度：12.51 mm
Base Number Matches：1

SN54LVTH182646AHV 数据手册

 浏览型号SN54LVTH182646AHV的Datasheet PDF文件第2页浏览型号SN54LVTH182646AHV的Datasheet PDF文件第3页浏览型号SN54LVTH182646AHV的Datasheet PDF文件第4页浏览型号SN54LVTH182646AHV的Datasheet PDF文件第5页浏览型号SN54LVTH182646AHV的Datasheet PDF文件第6页浏览型号SN54LVTH182646AHV的Datasheet PDF文件第7页 
SN54LVTH18646A, SN54LVTH182646A, SN74LVTH18646A, SN74LVTH182646A  
3.3-V ABT SCAN TEST DEVICES  
WITH 18-BIT TRANSCEIVERS AND REGISTERS  
SCBS311D – MARCH 1994 – REVISED JUNE 1997  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Compatible With IEEE Std 1149.1-1990  
(JTAG) Test Access Port and  
Boundary-Scan Architecture  
Members of the Texas Instruments  
Widebus Family  
SCOPE Instruction Set  
– IEEE Std 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
and Output Voltages With 3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
Include D-Type Flip-Flops and Control  
Circuitry to Provide Multiplexed  
Transmission of Stored and Real-Time Data  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
– Even-Parity Opcodes  
Packaged in 64-Pin Plastic Thin Quad Flat  
(PM) Packages Using 0.5-mm  
B-Port Outputs of ’LVTH182646A Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
Center-to-Center Spacings and 68-Pin  
Ceramic Quad Flat (HV) Packages Using  
25-mil Center-to-Center Spacings  
description  
The ’LVTH18646A and ’LVTH182646A scan test devices with 18-bit bus transceivers and registers are  
members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices  
supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan  
access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.  
Additionally, these devices are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed  
transmission of data directly from the input bus or from the internal registers. They can be used either as two  
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot  
samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating  
the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers  
and registers.  
Transceiver function is controlled by output-enable (OE) and direction (DIR) inputs. When OE is low, the  
transceiver is active and operates in the A-to-B direction when DIR is high or in the B-to-A direction when DIR  
is low. When OE is high, both the A and B outputs are in the high-impedance state, effectively isolating  
both buses.  
Data flow is controlled by clock (CLKAB and CLKBA) and select (SAB and SBA) inputs. Data on the A bus is  
clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data  
is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for  
presentation to the B bus (registered mode). The function of the CLKBA and SBA inputs mirrors that of CLKAB  
and SAB, respectively. Figure 1 shows the four fundamental bus-management functions that can be performed  
with the ’LVTH18646A and ’LVTH182646A.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...36

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