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SN54LVTH182514

更新时间： 2024-11-19 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器测试
页数 文件大小 规格书
34页 548K
描述
3.3-V ABT SCAN TEST DEVICES WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS

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SN54LVTH182514 数据手册

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SN54LVTH18514, SN54LVTH182514, SN74LVTH18514, SN74LVTH182514  
3.3-V ABT SCAN TEST DEVICES  
WITH 20-BIT UNIVERSAL BUS TRANSCEIVERS  
SCBS670C – AUGUST 1996 – REVISED MARCH 1998  
SN54LVTH18514, SN54LVTH182514 . . . HKC PACKAGE  
SN74LVTH18514, SN74LVTH182514 . . . DGG PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments (TI )  
SCOPE Family of Testability Products  
Members of the TI Widebus Family  
LEBA  
OEBA  
A1  
CLKBA  
CLKENBA  
B1  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
2
and Output Voltages With 3.3-V V  
)
3
CC  
A2  
B2  
4
Support Unregulated Battery Operation  
Down to 2.7 V  
A3  
GND  
A4  
B3  
GND  
B4  
5
6
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
7
A5  
A6  
B5  
B6  
8
9
V
V
10  
11  
CC  
CC  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A7  
B7  
A8 12  
A9 13  
53 B8  
52 B9  
B-Port Outputs of ’LVTH182514 Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
GND 14  
A10 15  
A11 16  
A12 17  
51 GND  
50 B10  
49 B11  
48 B12  
Compatible With the IEEE Std 1149.1-1990  
(JTAG) Test Access Port and  
Boundary-Scan Architecture  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
A13  
GND  
A14  
B13  
GND  
B14  
B15  
B16  
SCOPE Instruction Set  
– IEEE Std 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
A15  
A16  
V
V
CC  
CC  
A17  
A18  
A19  
B17  
B18  
B19  
GND  
A20  
GND  
B20  
CLKENAB  
CLKAB  
TDO  
OEAB  
LEAB  
TDI  
– Even-Parity Opcodes  
Package Options Include 64-Pin Plastic  
Thin Shrink Small-Outline (DGG) and 64-Pin  
Ceramic Dual Flat (HKC) Packages Using  
0.5-mm Center-to-Center Spacings  
TMS  
TCK  
description  
The ’LVTH18514 and ’LVTH182514 scan test devices with 20-bit universal bus transceivers are members of  
the TI SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990  
boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is  
accomplished via the 4-wire test access port (TAP) interface.  
Additionally, these devices are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, UBT, and TI are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...34

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