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SN54LVTH16245A_06

更新时间： 2024-11-05 05:04:55
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德州仪器 - TI 输出元件
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18页 487K
描述
3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54LVTH16245A_06 数据手册

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SN54LVTH16245A, SN74LVTH16245A  
3.3-V ABT 16-BIT BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCBS143R–MAY 1992–REVISED NOVEMBER 2006  
FEATURES  
SN54LVTH16245A . . . WD PACKAGE  
SN74LVTH16245A . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
Members of the Texas Instruments Widebus™  
Family  
•
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V Operation  
and Low Static-Power Dissipation  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
3
•
•
•
•
•
•
•
•
•
Support Mixed-Mode Signal Operation (5-V  
4
Input and Output Voltages With 3.3-V VCC  
)
5
Support Unregulated Battery Operation Down  
to 2.7 V  
6
7
V
CC  
V
CC  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Flow-Through Architecture Optimizes PCB  
Layout  
Ioff and Power-Up 3-State Support Hot  
Insertion  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
V
CC  
V
CC  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
2B5  
2B6  
GND  
2B7  
2B8  
2DIR  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
ESD Protection Exceeds JESD 22  
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
DESCRIPTION/ORDERING INFORMATION  
The 'LVTH16245A devices are 16-bit (dual-octal) noninverting 3-state transceivers designed for low-voltage  
(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.  
The devices are designed for asynchronous communication between two data buses. The logic levels of the  
direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port  
outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to  
the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are  
activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level  
applied to prevent excess ICC and ICCZ  
.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown  
resistors with the bus-hold circuitry is not recommended.  
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1992–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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