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SN54LVTH16241WD PDF预览

SN54LVTH16241WD

更新时间： 2024-11-04 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
9页 127K
描述
3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54LVTH16241WD 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：48
Reach Compliance Code：unknown风险等级：5.84
其他特性：OUTPUT ENABLE ACTIVE HIGH FOR TWO FUNCTIONS系列：LVT
JESD-30 代码：R-GDFP-F48长度：15.748 mm
逻辑集成电路类型：BUS DRIVER位数：4
功能数量：4端口数量：2
端子数量：48最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：4 ns
认证状态：Not Qualified座面最大高度：3.05 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：MILITARY
端子形式：FLAT端子节距：0.635 mm
端子位置：DUAL宽度：9.652 mm
Base Number Matches：1

SN54LVTH16241WD 数据手册

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SN54LVTH16241, SN74LVTH16241  
3.3-V ABT 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS693C – MAY 1997 – REVISED APRIL 1999  
SN54LVTH16241 . . . WD PACKAGE  
SN74LVTH16241 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1OE  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1
2
3
4
5
6
7
8
9
48 2OE  
47 1A1  
46 1A2  
45 GND  
44 1A3  
43 1A4  
Support Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
V
42  
V
CC  
CC  
2Y1  
2Y2  
41 2A1  
40 2A2  
39 GND  
38 2A3  
37 2A4  
36 3A1  
35 3A2  
34 GND  
33 3A3  
32 3A4  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
GND 10  
2Y3 11  
2Y4 12  
3Y1 13  
3Y2 14  
GND 15  
3Y3 16  
3Y4 17  
= 3.3 V, T = 25°C  
CC  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
18  
31  
V
CC  
CC  
Flow-Through Architecture Optimizes PCB  
Layout  
4Y1 19  
4Y2 20  
GND 21  
4Y3 22  
4Y4 23  
4OE 24  
30 4A1  
29 4A2  
28 GND  
27 4A3  
26 4A4  
25 3OE  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
The devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide  
noninverting outputs and complementary output-enable (OE and OE) inputs.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor  
CC  
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by  
the current-sinking/current-sourcing capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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