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SN54LVC32AWR PDF预览

SN54LVC32AWR

更新时间： 2024-11-23 21:09:51
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
8页 111K
描述
LVC/LCX/Z SERIES, QUAD 2-INPUT OR GATE, CDFP14, CERAMIC, FP-14

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SN54LVC32AWR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.58系列：LVC/LCX/Z
JESD-30 代码：R-GDFP-F14长度：9.21 mm
逻辑集成电路类型：OR GATE功能数量：4
输入次数：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：4.4 ns认证状态：Not Qualified
座面最大高度：2.03 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：2.7 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：6.29 mmBase Number Matches：1

SN54LVC32AWR 数据手册

 浏览型号SN54LVC32AWR的Datasheet PDF文件第2页浏览型号SN54LVC32AWR的Datasheet PDF文件第3页浏览型号SN54LVC32AWR的Datasheet PDF文件第4页浏览型号SN54LVC32AWR的Datasheet PDF文件第5页浏览型号SN54LVC32AWR的Datasheet PDF文件第6页浏览型号SN54LVC32AWR的Datasheet PDF文件第7页 
SN54LVC32A, SN74LVC32A  
QUADRUPLE 2-INPUT POSITIVE-OR GATES  
SCAS286H – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC32A . . . J OR W PACKAGE  
SN74LVC32A . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1Y  
2A  
2B  
10 3B  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
2Y  
9
8
3A  
3Y  
= 3.3 V, T = 25°C  
CC  
A
GND  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
SN54LVC32A . . . FK PACKAGE  
(TOP VIEW)  
Inputs Accept Voltages to 5.5 V  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and DIPs (J)  
3
2
1
20 19  
18  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
15  
14  
description  
NC  
2B  
The SN54LVC32A quadruple 2-input positive-OR  
gate is designed for 2.7-V to 3.6-V V operation  
9 10 11 12 13  
CC  
and the SN74LVC32A quadruple 2-input positive-  
OR gate is designed for 1.65-V to 3.6-V V  
operation.  
CC  
NC – No internal connection  
The ’LVC32A devices perform the Boolean  
function Y  
logic.  
A
B or Y  
A • B in positive  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN54LVC32A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LVC32A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
X
H
L
H
X
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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