5秒后页面跳转
捷配首页

Datasheet > SN54LVC374AFKR
SN54LVC374AFKR PDF预览

SN54LVC374AFKR

更新时间： 2024-11-26 21:01:39
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
9页 127K
描述
LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20

阅读下载

中文翻译

获取价格

SN54LVC374AFKR 技术参数

生命周期：Obsolete包装说明：QCCN,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.56系列：LVC/LCX/Z
JESD-30 代码：S-CQCC-N20长度：8.89 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装形状：SQUARE
封装形式：CHIP CARRIER传播延迟（tpd）：9.5 ns
认证状态：Not Qualified座面最大高度：2.03 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD宽度：8.89 mm
Base Number Matches：1

SN54LVC374AFKR 数据手册

 浏览型号SN54LVC374AFKR的Datasheet PDF文件第2页浏览型号SN54LVC374AFKR的Datasheet PDF文件第3页浏览型号SN54LVC374AFKR的Datasheet PDF文件第4页浏览型号SN54LVC374AFKR的Datasheet PDF文件第5页浏览型号SN54LVC374AFKR的Datasheet PDF文件第6页浏览型号SN54LVC374AFKR的Datasheet PDF文件第7页 
SN54LVC374A, SN74LVC374A  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCAS296I – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC374A . . . J OR W PACKAGE  
SN74LVC374A . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
CC  
A
1
2
3
4
5
6
7
8
9
20  
19  
18  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
Power Off Disables Inputs/Outputs,  
Permitting Live Insertion  
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
GND 10  
SN54LVC374A . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and DIPs (J)  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
description  
14 6D  
9 10 11 12 13  
The SN54LVC374A octal edge-triggered D-type  
flip-flop is designed for 2.7-V to 3.6-V V  
CC  
operation and the SN74LVC374A octal  
edge-triggered D-type flip-flop is designed for  
1.65-V to 3.6-V V  
operation.  
CC  
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output  
(I/O) ports, bidirectional bus drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data  
(D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

与SN54LVC374AFKR相关器件

型号 品牌 获取价格 描述 数据表
SN54LVC374AJ TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC374AW TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC374AWR TI

获取价格

 		暂无描述
SN54LVC41A TI

获取价格

 		HEX SCHMITT-TRIGGER INVERTERS
SN54LVC540A TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54LVC540A_06 TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54LVC540A_16 TI

获取价格

 		Octal Buffers/Drivers with 3-State Outputs
SN54LVC540AFK TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54LVC540AJ TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54LVC540AW TI

获取价格

 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

与SN54LVC374AFKR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证