5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN54LVC373A
SN54LVC373A PDF预览

SN54LVC373A

更新时间： 2024-11-05 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
9页 129K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN54LVC373A 数据手册

 浏览型号SN54LVC373A的Datasheet PDF文件第2页浏览型号SN54LVC373A的Datasheet PDF文件第3页浏览型号SN54LVC373A的Datasheet PDF文件第4页浏览型号SN54LVC373A的Datasheet PDF文件第5页浏览型号SN54LVC373A的Datasheet PDF文件第6页浏览型号SN54LVC373A的Datasheet PDF文件第7页 
SN54LVC373A, SN74LVC373A  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCAS295J – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC373A . . . J OR W PACKAGE  
SN74LVC373A . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
CC  
A
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 LE  
Power Off Disables Outputs, Permitting  
Live Insertion  
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
GND 10  
SN54LVC373A . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Packages, and DIPs (J)  
3
2
1 20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
description  
14 6D  
9 10 11 12 13  
TheSN54LVC373AoctaltransparentD-typelatch  
is designed for 2.7-V to 3.6-V V operation and  
CC  
the SN74LVC373A octal transparent D-type latch  
is designed for 1.65-V to 3.6-V V operation.  
CC  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the  
Q outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54LVC373A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LVC373A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

SN54LVC373A 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC373A-EP TI

功能相似

 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC373A-Q1 TI

功能相似

 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC373A TI

功能相似

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

与SN54LVC373A相关器件

型号 品牌 获取价格 描述 数据表
SN54LVC373A_07 TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC373A_10 TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC373AFK TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC373AJ TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC373AW TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC374A TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC374A_07 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC374A_09 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC374AFK TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC374AFKR TI

获取价格

 		LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20

与SN54LVC373A相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证