SN54LVC573A

更新时间： 2024-11-22 23:03:07

品牌	Logo	应用领域
德州仪器 - TI		锁存器输出元件
页数	文件大小	规格书
9页	130K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN54LVC573A 数据手册

SN54LVC573A, SN74LVC573A

OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCAS300I – JANUARY 1993 – REVISED JUNE 1998

SN54LVC573A . . . J OR W PACKAGE

SN74LVC573A . . . DB, DW, OR PW PACKAGE

(TOP VIEW)

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

Typical V

> 2 V at V

(Output V

Undershoot)

OHV

= 3.3 V, T = 25°C

Support Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

)

Power Off Disables Outputs, Permitting

Live Insertion

13 7Q

12 8Q

11 LE

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

GND 10

SN54LVC573A . . . FK PACKAGE

(TOP VIEW)

Latch-Up Performance Exceeds 250 mA Per

JESD 17

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), Thin Shrink Small-Outline (PW), and

Ceramic Flat (W) Packages, Ceramic Chip

Carriers (FK), and DIPs (J)

1 20 19

description

9 10 11 12 13

TheSN54LVC573AoctaltransparentD-typelatch

is designed for 2.7-V to 3.6-V V operation and

the SN74LVC573A octal transparent D-type latch

is designed for 1.65-V to 3.6-V V operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,

bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the

Q outputs are latched at the logic levels at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

中文翻译

下载PDF

与SN54LVC573A相关器件

型号	品牌	获取价格	描述	数据表
SN54LVC573A_10	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC573AFK	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC573AFKR	TI	获取价格	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
SN54LVC573AJ	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC573AW	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54LVC573AWR	TI	获取价格	LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, FP-20
SN54LVC574	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574A	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574A_10	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54LVC574AFK	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

与SN54LVC573A相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

36
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

28
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

56
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

53

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54LVC573A

SN54LVC573A 数据手册

与SN54LVC573A相关器件

与SN54LVC573A相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54LVC573A

SN54LVC573A 数据手册

与SN54LVC573A相关器件

与SN54LVC573A相关文章

您还可以找

您在本页遇到什么问题？