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SN54HCT273FKR PDF预览

SN54HCT273FKR

更新时间: 2024-11-24 13:13:43
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
6页 116K
描述
HCT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20

SN54HCT273FKR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.73系列:HCT
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):50 ns认证状态:Not Qualified
座面最大高度:2.03 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
触发器类型:POSITIVE EDGE宽度:8.89 mm
最小 fmax:19 MHzBase Number Matches:1

SN54HCT273FKR 数据手册

 浏览型号SN54HCT273FKR的Datasheet PDF文件第2页浏览型号SN54HCT273FKR的Datasheet PDF文件第3页浏览型号SN54HCT273FKR的Datasheet PDF文件第4页浏览型号SN54HCT273FKR的Datasheet PDF文件第5页浏览型号SN54HCT273FKR的Datasheet PDF文件第6页 
SN54HCT273, SN74HCT273  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLEAR  
SCLS068C – NOVEMBER 1988 – REVISED MAY 1997  
SN54HCT273 . . . J OR W PACKAGE  
SN74HCT273 . . . DW, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Contain Eight D-Type Flip-Flops  
Direct Clear Input  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CLR  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
– Pattern Generators  
Package Options Include Plastic  
Small-Outline (DW) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
GND  
description  
SN54HCT273 . . . FK PACKAGE  
(TOP VIEW)  
Thesedevicesarepositive-edge-triggeredD-type  
flip-flops with a common enable input. The  
’HCT273 are similar to the ’HCT377, but feature  
a common clear enable (CLR) input instead of a  
latched clock.  
3
2
1
20 19  
18  
4
5
6
7
8
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a  
particular voltage level and is not directly related  
to the positive-going pulse. When CLK is at either  
the high or low level, the D input has no effect at  
the output. The circuits are designed to prevent  
false clocking by transitions at CLR.  
17  
16  
15  
14  
9 10 11 12 13  
The SN54HCT273 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HCT273 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLR  
L
CLK  
D
X
H
L
X
L
H
L
H
H
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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