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SN54HCT32FK PDF预览

SN54HCT32FK

更新时间: 2024-11-23 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
4页 80K
描述
QUADRUPLE 2-INPUT POSITIVE-OR GATES

SN54HCT32FK 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:CERAMIC, LCC-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
系列:HCTJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:5 VProp。Delay @ Nom-Sup:35 ns
传播延迟(tpd):35 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2.03 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
宽度:8.89 mmBase Number Matches:1

SN54HCT32FK 数据手册

 浏览型号SN54HCT32FK的Datasheet PDF文件第2页浏览型号SN54HCT32FK的Datasheet PDF文件第3页浏览型号SN54HCT32FK的Datasheet PDF文件第4页 
SN54HCT32, SN74HCT32  
QUADRUPLE 2-INPUT POSITIVE-OR GATES  
SCLS064B – NOVEMBER 1988 – REVISED MAY 1997  
SN54HCT32 . . . J OR W PACKAGE  
SN74HCT32 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
and Ceramic Flat (W) Packages,  
Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
1Y  
2A  
2B  
10 3B  
9
8
2Y  
3A  
3Y  
description  
GND  
The ’HCT32 contain four independent 2-input OR  
gates. They perform the Boolean function  
SN54HCT32 . . . FK PACKAGE  
(TOP VIEW)  
Y
A B or Y  
A
B
in positive logic.  
The SN54HCT32 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HCT32 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
FUNCTION TABLE  
(each gate)  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
3B  
INPUTS  
OUTPUT  
Y
A
B
X
H
L
H
X
L
H
H
L
NC – No internal connection  
logic symbol  
1
1A  
2
1  
3
1Y  
1B  
4
2A  
5
6
2Y  
2B  
9
3A  
8
10  
3Y  
3B  
4A  
4B  
12  
13  
11  
4Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, DB, J, N, PW, and W packages.  
logic diagram (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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