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SN54HCT373J-00 PDF预览

SN54HCT373J-00

更新时间： 2024-11-20 19:57:07
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
21页 1148K
描述
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20

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中文翻译

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SN54HCT373J-00 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.09系列：HCT
JESD-30 代码：R-GDIP-T20长度：24.195 mm
负载电容（CL）：150 pF逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
传播延迟（tpd）：79 ns认证状态：Not Qualified
座面最大高度：5.08 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN54HCT373J-00 数据手册

 浏览型号SN54HCT373J-00的Datasheet PDF文件第2页浏览型号SN54HCT373J-00的Datasheet PDF文件第3页浏览型号SN54HCT373J-00的Datasheet PDF文件第4页浏览型号SN54HCT373J-00的Datasheet PDF文件第5页浏览型号SN54HCT373J-00的Datasheet PDF文件第6页浏览型号SN54HCT373J-00的Datasheet PDF文件第7页 
SN54HCT373, SN74HCT373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS009D – MARCH 1984 – REVISED AUGUST 2003  
SN54HCT373 . . .J OR W PACKAGE  
SN74HCT373 . . .DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Operating Voltage Range of 4.5 V to 5.5 V  
High-Current 3-State True Outputs Can  
Drive Up To 15 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
Typical t = 21 ns  
pd  
6-mA Output Drive at 5 V  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
CC  
17 7D  
16 7Q  
15 6Q  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
Eight High-Current Latches in a Single  
Package  
14  
6D  
13 5D  
12 5Q  
11 LE  
Full Parallel Access for Loading  
GND 10  
description/ordering information  
SN54HCT373 . . .FK PACKAGE  
(TOP VIEW)  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
The eight latches of the ’HCT373 devices are  
transparent  
D-type  
latches.  
While  
the  
15 6Q  
14  
9 10 11 12 13  
latch-enable (LE) input is high, the Q outputs  
follow the data (D) inputs. When LE is taken low,  
the Q outputs are latched at the levels that were  
set up at the D inputs.  
6D  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HCT373N  
SN74HCT373N  
SN74HCT373DW  
SN74HCT373DWR  
SN74HCT373NSR  
SN74HCT373DBR  
SN74HCT373PW  
SN74HCT373PWR  
SN74HCT373PWT  
SNJ54HCT373J  
SOIC – DW  
HCT373  
SOP – NS  
HCT373  
HT373  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HT373  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HCT373J  
SNJ54HCT373W  
–55°C to 125°C  
SNJ54HCT373W  
SNJ54HCT373FK  
SNJ54HCT373FK  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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