5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 触发器/锁存器> SN54HC112FK
SN54HC112FK PDF预览

SN54HC112FK

更新时间： 2024-09-12 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
7页 97K
描述
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

阅读下载

中文翻译

获取价格

SN54HC112FK 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：QCCN, LCC20,.35SQ
针数：20Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.67
系列：HC/UHJESD-30 代码：S-CQCC-N20
长度：8.89 mm负载电容（CL）：50 pF
逻辑集成电路类型：J-K FLIP-FLOP最大频率@ Nom-Sup：20000000 Hz
最大I（ol）：0.0052 A位数：2
功能数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC20,.35SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/6 V
传播延迟（tpd）：185 ns认证状态：Not Qualified
座面最大高度：2.03 mm子类别：FF/Latches
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：NEGATIVE EDGE宽度：8.89 mm
最小 fmax：20 MHzBase Number Matches：1

SN54HC112FK 数据手册

 浏览型号SN54HC112FK的Datasheet PDF文件第2页浏览型号SN54HC112FK的Datasheet PDF文件第3页浏览型号SN54HC112FK的Datasheet PDF文件第4页浏览型号SN54HC112FK的Datasheet PDF文件第5页浏览型号SN54HC112FK的Datasheet PDF文件第6页浏览型号SN54HC112FK的Datasheet PDF文件第7页 
SN54HC112, SN74HC112  
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCLS099C – DECEMBER 1982 – REVISED APRIL 1999  
SN54HC112 . . . J OR W PACKAGE  
SN74HC112 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J) DIPs  
1CLK  
1K  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
1CLR  
2CLR  
2CLK  
description  
1J  
1PRE  
1Q  
The ’HC112 devices contain two independent J-K  
negative-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the J and K inputs meeting the  
setup time requirements are transferred to the  
outputs on the negative-going edge of the clock  
(CLK) pulse. Clock triggering occurs at a voltage  
level and is not directly related to the rise time of  
CLK. Following the hold-time interval, data at the  
J and K inputs may be changed without affecting  
the levels at the outputs. These versatile flip-flops  
perform as toggle flip-flops by tying J and K high.  
12 2K  
11  
10  
9
1Q  
2J  
2Q  
2PRE  
2Q  
GND  
SN54HC112 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2CLR  
2CLK  
NC  
1J  
1PRE  
NC  
4
5
6
7
8
17  
16  
The SN54HC112 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HC112 is characterized for  
operation from –40°C to 85°C.  
15 2K  
14  
9 10 11 12 13  
1Q  
2J  
1Q  
NC – No internal connection  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
†
H
†
L
L
X
H
H
H
↓
Q
Q
0
0
H
H
↓
H
L
L
H
L
H
H
↓
H
H
X
L
H
H
H
↓
H
X
Toggle  
H
H
H
Q
Q
0
0
†
This configuration is unstable; that is, it does not persist  
when either PRE or CLR returns to its inactive (high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

中文翻译

下载PDF

与SN54HC112FK相关器件

型号 品牌 获取价格 描述 数据表
SN54HC112FK-00 TI

获取价格

 		HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
SN54HC112FKR TI

获取价格

 		HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, CE
SN54HC112J TI

获取价格

 		DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54HC112J-00 TI

获取价格

 		HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
SN54HC112W TI

获取价格

 		DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN54HC112WR TI

获取价格

 		HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CE
SN54HC114 TI

获取价格

 		DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK
SN54HC114J TI

获取价格

 		IC,FLIP-FLOP,DUAL,J/K TYPE,HC-CMOS,DIP,14PIN,CERAMIC
SN54HC114J-00 TI

获取价格

 		HC/UH SERIES, NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
SN54HC11FK TI

获取价格

 		TRIPLE 3-INPUT POSITIVE-AND GATES

与SN54HC112FK相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证