5秒后页面跳转
SN54HC126_08 PDF预览

SN54HC126_08

更新时间: 2024-11-01 05:05:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
17页 636K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN54HC126_08 数据手册

 浏览型号SN54HC126_08的Datasheet PDF文件第2页浏览型号SN54HC126_08的Datasheet PDF文件第3页浏览型号SN54HC126_08的Datasheet PDF文件第4页浏览型号SN54HC126_08的Datasheet PDF文件第5页浏览型号SN54HC126_08的Datasheet PDF文件第6页浏览型号SN54HC126_08的Datasheet PDF文件第7页 
ꢋ ꢌꢍꢎꢏ ꢌꢐꢑ ꢒ ꢓꢌꢀ ꢓꢌꢔ ꢔ ꢒꢏ ꢕ ꢍꢖꢒ  
SCLS103E − MARCH 1984 − REVISED JULY 2003  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
D
D
Typical t = 11 ns  
pd  
6-mA Output Drive at 5 V  
High-Current 3-State Outputs Interface  
Directly With System Bus or Can Drive Up  
To 15 LSTTL Loads  
Low Input Current of 1 µA Max  
D
Low Power Consumption, 80-µA Max I  
CC  
SN54HC126 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC126 . . . J OR W PACKAGE  
SN74HC126 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
1OE  
1A  
V
CC  
13 4OE  
1
2
3
4
5
6
7
14  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
12  
11  
10  
9
1Y  
4A  
17  
16  
2OE  
2A  
4Y  
2OE  
NC  
3OE  
3A  
15 NC  
14  
9 10 11 12 13  
2Y  
3OE  
2A  
8
GND  
3Y  
NC − No internal connection  
description/ordering information  
These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled  
when the associated output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup  
resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC126N  
SN74HC126N  
SN74HC126D  
SN74HC126DR  
SN74HC126DT  
SN74HC126NSR  
SN74HC126DBR  
SN74HC126PW  
SN74HC126PWR  
SN74HC126PWT  
SNJ54HC126J  
SNJ54HC126W  
SNJ54HC126FK  
HC126  
SOP − NS  
HC126  
HC126  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC126  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC126J  
SNJ54HC126W  
SNJ54HC126FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢛ ꢝ ꢨ ꢠ ꢟꢫ ꢦꢥ ꢣꢤ ꢥꢟ ꢡꢨ ꢪꢜ ꢢꢝ ꢣ ꢣꢟ ꢲꢘ ꢑꢚ ꢐꢏ ꢔ ꢚꢙꢳꢂ ꢙꢂꢉ ꢢꢪꢪ ꢨꢢ ꢠ ꢢ ꢡꢧ ꢣꢧꢠ ꢤ ꢢ ꢠ ꢧ ꢣꢧ ꢤꢣꢧ ꢫ  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
ꢦ ꢝꢪ ꢧꢤꢤ ꢟ ꢣꢭꢧ ꢠ ꢯꢜ ꢤꢧ ꢝ ꢟꢣꢧ ꢫꢬ ꢛ ꢝ ꢢꢪ ꢪ ꢟ ꢣꢭꢧ ꢠ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢤ ꢉ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢜꢟ ꢝ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

与SN54HC126_08相关器件

型号 品牌 获取价格 描述 数据表
SN54HC126_15 TI

获取价格

QUADRUPLE BUSBUFFER GATES WITH 3-STATE OUTPUTS
SN54HC126FH TI

获取价格

IC,BUFFER/DRIVER,SINGLE,4-BIT,HC-CMOS,LLCC,20PIN,CERAMIC
SN54HC126FK TI

获取价格

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54HC126FK-00 TI

获取价格

HC/UH SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CQCC20
SN54HC126J TI

获取价格

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54HC126W TI

获取价格

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54HC126WR TI

获取价格

HC/UH SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDFP14, CERAMIC, DFP-14
SN54HC132 TI

获取价格

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SN54HC132-DIE TI

获取价格

4 通道、2 输入、2V 至 6V 与非门
SN54HC132FK TI

获取价格

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS