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SN54HC126FH PDF预览

SN54HC126FH

更新时间: 2024-11-20 13:13:43
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
6页 82K
描述
IC,BUFFER/DRIVER,SINGLE,4-BIT,HC-CMOS,LLCC,20PIN,CERAMIC

SN54HC126FH 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCN, LCC20,.35SQReach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.89
控制类型:ENABLE HIGHJESD-30 代码:S-XQCC-N20
逻辑集成电路类型:BUS DRIVER位数:4
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V认证状态:Not Qualified
子类别:Bus Driver/Transceivers表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

SN54HC126FH 数据手册

 浏览型号SN54HC126FH的Datasheet PDF文件第2页浏览型号SN54HC126FH的Datasheet PDF文件第3页浏览型号SN54HC126FH的Datasheet PDF文件第4页浏览型号SN54HC126FH的Datasheet PDF文件第5页浏览型号SN54HC126FH的Datasheet PDF文件第6页 
SN54HC126, SN74HC126  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS103C – MARCH 1984 – REVISED FEBRUARY 1999  
SN54HC126 . . . J OR W PACKAGE  
SN74HC126 . . . D, DB, OR N PACKAGE  
(TOP VIEW)  
High-Current 3-State Outputs Interface  
Directly With System Bus or Can Drive up  
to 15 LSTTL Loads  
Package Options Include Plastic  
1OE  
1A  
V
CC  
4OE  
4A  
1
2
3
4
5
6
7
14  
13  
12  
11  
Small-Outline (D), Shrink Small-Outline  
(DB), and Ceramic Flat (W) Packages,  
Ceramic Chip Carriers (FK), and Standard  
Plastic (N) and Ceramic (J) DIPs  
1Y  
2OE  
2A  
4Y  
10 3OE  
2Y  
9
8
3A  
3Y  
description  
GND  
These quadruple bus buffer gates feature  
independent line drivers with 3-state outputs.  
Each output is disabled when the associated  
output-enable (OE) input is low.  
SN54HC126 . . . FK PACKAGE  
(TOP VIEW)  
The SN54HC126 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HC126 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
17  
16  
2OE  
NC  
FUNCTION TABLE  
(each buffer)  
15 NC  
14  
9 10 11 12 13  
3OE  
2A  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
H
H
L
H
L
NC – No internal connection  
X
Z
logic symbol  
1
1OE  
EN  
3
1Y  
2
1A  
4
6
2OE  
5
2Y  
2A  
10  
8
3OE  
3A  
3Y  
9
13  
12  
4OE  
11  
4Y  
4A  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, DB, J, N, and W packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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