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SN54AHC573_16

更新时间： 2024-11-03 02:58:35
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德州仪器 - TI /
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18页 575K
描述
Octal Transparent D-Type Latches With 3-State Outputs

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SN54AHC573_16 数据手册

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ꢓ ꢔꢋ ꢅ ꢈ ꢑꢀꢋꢄꢋ ꢏ ꢊ ꢕꢋ ꢎꢕ ꢋ  
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
SN54AHC573 . . . J OR W PACKAGE  
SN74AHC573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
Operating Range 2-V to 5.5-V V  
CC  
3-State Outputs Directly Drive Bus Lines  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
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18  
17  
16  
15  
14  
13  
12  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
description/ordering information  
The ’AHC573 devices are octal transparent  
D-type latches designed for 2-V to 5.5-V V  
operation.  
CC  
When the latch-enable (LE) input is high, the  
Q outputs follow the data (D) inputs. When LE is  
low, the Q outputs are latched at the logic levels  
of the D inputs.  
GND 10  
11 LE  
SN54AHC573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
OE does not affect the internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
9 10 11 12 13  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AHC573N  
SN74AHC573N  
Tube  
SN74AHC573DW  
SN74AHC573DWR  
SN74AHC573NSR  
SN74AHC573DBR  
SN74AHC573PW  
SN74AHC573PWR  
SN74AHC573DGVR  
SNJ54AHC573J  
SOIC − DW  
AHC573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AHC573  
HA573  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HA573  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − J  
HA573  
SNJ54AHC573J  
SNJ54AHC573W  
SNJ54AHC573FK  
CFP − W  
Tube  
SNJ54AHC573W  
SNJ54AHC573FK  
−55°C to 125°C  
LCCC − FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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