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SN54AHC595J PDF预览

SN54AHC595J

更新时间： 2024-11-01 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路输出元件
页数 文件大小 规格书
17页 444K
描述
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

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中文翻译

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SN54AHC595J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
其他特性：PARALLEL OUTPUT IS REGISTERED计数方向：RIGHT
系列：AHCJESD-30 代码：R-GDIP-T16
长度：19.56 mm逻辑集成电路类型：SERIAL IN PARALLEL OUT
位数：8功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：18.5 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：115 MHz
Base Number Matches：1

SN54AHC595J 数据手册

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SCLS373I − MAY 1997 − REVISED JUNE 2004  
SN54AHC595 . . . J OR W PACKAGE  
SN74AHC595 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
Operating Range 2-V to 5.5-V V  
CC  
8-Bit Serial-In, Parallel-Out Shift  
Shift Register Has Direct Clear  
Q
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
B
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Q
C
D
A
Q
SER  
OE  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Q
E
Q
12 RCLK  
F
11  
10  
9
Q
SRCLK  
SRCLR  
G
− 1000-V Charged-Device Model (C101)  
Q
H
GND  
Q
H′  
description/ordering information  
The ’AHC595 devices contain an 8-bit serial-in,  
parallel-out shift register that feeds an 8-bit D-type  
storage register. The storage register has parallel  
3-state outputs. Separate clocks are provided for  
both the shift and storage registers. The shift  
register has a direct overriding clear (SRCLR)  
input, serial (SER) input, and a serial output for  
cascading. When the output-enable (OE) input is  
SN54AHC595 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18  
SER  
OE  
Q
4
5
6
7
8
D
Q
17  
16  
E
NC  
NC  
high, all outputs, except Q , are in the  
H′  
15 RCLK  
14  
9 10 11 12 13  
Q
F
high-impedance state.  
SRCLK  
Q
G
Both the shift-register clock (SRCLK) and  
storage-register clock (RCLK) are positive-edge  
triggered. If both clocks are connected together,  
the shift register always is one clock pulse ahead  
of the storage register.  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube  
SN74AHC595N  
SN74AHC595N  
Tube  
SN74AHC595D  
AHC595  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHC595DR  
SN74AHC595NSR  
SN74AHC595DBR  
SN74AHC595PW  
SN74AHC595PWR  
SNJ54AHC959J  
SNJ54AHC595W  
SNJ54AHC595FK  
−40°C to 85°C  
SOP − NS  
AHC595  
HA595  
SSOP − DB  
TSSOP − PW  
HA595  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54AHC595J  
SNJ54AHC595W  
SNJ54AHC595FK  
Tube  
−55°C to 125°C  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

中文翻译

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