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SN54AHC595WR PDF预览

SN54AHC595WR

更新时间： 2024-11-02 20:49:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 163K
描述
AHC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP16, CERAMIC, FP-16

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SN54AHC595WR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84其他特性：PARALLEL OUTPUT IS REGISTERED
计数方向：RIGHT系列：AHC
JESD-30 代码：R-GDFP-F16长度：10.2 mm
逻辑集成电路类型：SERIAL IN PARALLEL OUT位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装形状：RECTANGULAR封装形式：FLATPACK
传播延迟（tpd）：18.5 ns认证状态：Not Qualified
座面最大高度：2.03 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：6.73 mm
最小 fmax：115 MHzBase Number Matches：1

SN54AHC595WR 数据手册

 浏览型号SN54AHC595WR的Datasheet PDF文件第2页浏览型号SN54AHC595WR的Datasheet PDF文件第3页浏览型号SN54AHC595WR的Datasheet PDF文件第4页浏览型号SN54AHC595WR的Datasheet PDF文件第5页浏览型号SN54AHC595WR的Datasheet PDF文件第6页浏览型号SN54AHC595WR的Datasheet PDF文件第7页 
SN54AHC595, SN74AHC595  
8-BIT SHIFT REGISTERS  
WITH 3-STATE OUTPUT REGISTERS  
SCLS373D – MAY 1997 – REVISED NOVEMBER 1999  
SN54AHC595 . . . J OR W PACKAGE  
SN74AHC595 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Operating Range 2-V to 5.5-V V  
CC  
Q
Q
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
8-Bit Serial-In, Parallel-Out Shift  
Shift Register Has Direct Clear  
B
Q
C
D
A
Q
SER  
OE  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Q
E
Q
12 RCLK  
F
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
11  
10  
9
Q
SRCLK  
SRCLR  
G
Q
H
GND  
Q
H′  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) DIPs  
SN54AHC595 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18  
SER  
OE  
Q
4
5
6
7
8
D
description  
Q
17  
16  
E
The ’AHC595 devices contain an 8-bit serial-in,  
parallel-out shift register that feeds an 8-bit D-type  
storage register. The storage register has parallel  
3-state outputs. Separate clocks are provided for  
both the shift and storage registers. The shift  
register has a direct overriding clear (SRCLR)  
input, serial (SER) input, and a serial output for  
cascading. When the output-enable (OE) input is  
NC  
NC  
15 RCLK  
14  
9 10 11 12 13  
Q
F
SRCLK  
Q
G
NC – No internal connection  
high, all outputs, except Q , are in the  
H′  
high-impedance state.  
Both the shift-register clock (SRCLK) and storage-register clock (RCLK) are positive-edge triggered. If both  
clocks are connected together, the shift register is always one clock pulse ahead of the storage register.  
The SN54AHC595 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHC595 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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