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SN54AC10FK PDF预览

SN54AC10FK

更新时间: 2024-10-31 22:39:47
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
5页 84K
描述
TRIPLE 3-INPUT POSITIVE-NAND GATES

SN54AC10FK 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC20,.35SQ
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.46
系列:ACJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.012 A
功能数量:3输入次数:3
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
Prop。Delay @ Nom-Sup:11 ns传播延迟(tpd):7 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.03 mm子类别:Gates
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mm

SN54AC10FK 数据手册

 浏览型号SN54AC10FK的Datasheet PDF文件第2页浏览型号SN54AC10FK的Datasheet PDF文件第3页浏览型号SN54AC10FK的Datasheet PDF文件第4页浏览型号SN54AC10FK的Datasheet PDF文件第5页 
SN54AC10, SN74AC10  
TRIPLE 3-INPUT POSITIVE-NAND GATES  
SCAS529B – AUGUST 1995 – REVISED SEPTEMBER 1996  
SN54AC10 . . . J OR W PACKAGE  
SN74AC10 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK) and  
Flatpacks (W), and Standard Plastic (N) and  
Ceramic (J) DIPS  
1A  
1B  
2A  
2B  
2C  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1C  
1Y  
3A  
3B  
3C  
3Y  
2Y  
GND  
description  
8
The ’AC10 contain three independent 3-input  
NAND gates. The devices perform the Boolean  
function Y = A B C or Y = A + B + C in positive  
logic.  
SN54AC10 . . . FK PACKAGE  
(TOP VIEW)  
The SN54AC10 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74AC10 is characterized for  
operation from 40°C to 85°C.  
3
2
1
20 19  
18  
1Y  
NC  
3A  
NC  
3B  
2A  
NC  
2B  
4
5
6
7
8
17  
16  
15  
14  
FUNCTION TABLE  
(each gate)  
NC  
2C  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
C
H
X
X
L
9 10 11 12 13  
L
H
H
H
X
X
NC – No internal connection  
X
logic symbol  
logic diagram, each gate (positive logic)  
1
1A  
1
1A  
&
12  
2
12  
6
1Y  
1B  
1C  
2
1Y  
2Y  
3Y  
13  
1B  
13  
1C  
3
4
5
2A  
2B  
2C  
3
6
2A  
4
2Y  
3Y  
2B  
5
11  
10  
9
2C  
3A  
3B  
3C  
8
8
11  
3A  
10  
3B  
9
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, DB, J, N, PW, and W packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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