Datasheet > SN54AC11109J

SN54AC11109J

更新时间： 2024-09-16 10:30:19

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
7页	89K
描述
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN54AC11109J 数据手册

54AC11109, 74AC11109

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCAS450 – MARCH 1987 – REVISED APRIL 1993

54AC11109 . . . J PACKAGE

74AC11109 . . . D OR N PACKAGE

(TOP VIEW)

• Flow-Through Architecture Optimizes

PCB Layout

• Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

1PRE

GND

2PRE

2CLK

1CLK

• EPIC (Enhanced-Performance Implanted

CMOS) 1-µm Process

• 500-mA Typical Latch-Up Immunity

at 125°C

1CLR

2CLR

• ESD Protection Exceeds 2000 V,

MIL STD-883C Method 3015

• Package Options Include Plastic

Small-Outline Packages, Ceramic Chip

Carriers, and Standard Plastic and Ceramic

300-mil DIPs

54AC11109 . . . FK PACKAGE

(TOP VIEW)

description

These devices contain two independent J-K

positive-edge-triggered flip-flops. A low level at

the preset (PRE) or clear (CLR) inputs sets or

resets the outputs regardless of the levels of the

other inputs. When preset and clear are inactive

(high), dataattheJandKinputsmeetingthesetup

time requirements are transferred to the outputs

on the positive-going edge of the clock pulse.

Clocktriggeringoccursatavoltagelevelandisnot

directly related to the rise time of the clock pulse.

Following the hold time interval, data at the J and

K inputs may be changed without affecting the

levels at the outputs. These versatile flip-flops can

perform as toggle flip-flops by grounding K and

tying J high. They also can perform as D-type

flip-flops by tying the J and K inputs together.

20 19

17 2K

1CLK

2CLK

2PRE

1PRE

9 10 11 12 13

NC – No internal connection

The 54AC11109 is characterized for operation over the full military temperature range of –55°C to 125°C. The

74AC11109 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUTS

PRE

CLK

CLR

†

↑

Toggle

↑

†

Thisconfigurationisnonstable;thatis, itwillnotpersistwhen

either PRE or CLR returns to its inactive (high) level.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

中文翻译

下载PDF

与SN54AC11109J相关器件

型号	品牌	获取价格	描述	数据表
SN54AC11FK	TI	获取价格	TRIPLE 3-INPUT POSITIVE-AND GATES
SN54AC11J	TI	获取价格	TRIPLE 3-INPUT POSITIVE-AND GATES
SN54AC11W	TI	获取价格	TRIPLE 3-INPUT POSITIVE-AND GATES
SN54AC14	TI	获取价格	HEX SCHMITT-TRIGGER INVERTERS
SN54AC14_07	TI	获取价格	HEX SCHMITT-TRIGGER INVERTERS
SN54AC14FK	TI	获取价格	HEX SCHMITT-TRIGGER INVERTERS
SN54AC14J	TI	获取价格	HEX SCHMITT-TRIGGER INVERTERS
SN54AC14-SP	TI	获取价格	RAD-TOLERANT CLASS V, HEX SCHMITT-TRIGGER INVERTER
SN54AC14W	TI	获取价格	HEX SCHMITT-TRIGGER INVERTERS
SN54AC240	TI	获取价格	OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

与SN54AC11109J相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

5
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

5
SL74HC10N：高性能三输入与非门解析
2024-09-03

83
AIC1781A 电池充电控制器深度解析
2024-09-03

76

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54AC11109J

SN54AC11109J 数据手册

与SN54AC11109J相关器件

与SN54AC11109J相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54AC11109J

SN54AC11109J 数据手册

与SN54AC11109J相关器件

与SN54AC11109J相关文章

您还可以找

您在本页遇到什么问题？