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SN54AC11109FK

更新时间： 2024-11-18 14:44:51
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 89K
描述
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, LCC-20

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SN54AC11109FK 技术参数

生命周期：Obsolete零件包装代码：QLCC
包装说明：LCC-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
系列：ACJESD-30 代码：S-CQCC-N20
长度：8.89 mm逻辑集成电路类型：J-KBAR FLIP-FLOP
位数：2功能数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
传播延迟（tpd）：13.5 ns认证状态：Not Qualified
座面最大高度：2.03 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
触发器类型：POSITIVE EDGE宽度：8.89 mm
最小 fmax：70 MHzBase Number Matches：1

SN54AC11109FK 数据手册

 浏览型号SN54AC11109FK的Datasheet PDF文件第2页浏览型号SN54AC11109FK的Datasheet PDF文件第3页浏览型号SN54AC11109FK的Datasheet PDF文件第4页浏览型号SN54AC11109FK的Datasheet PDF文件第5页浏览型号SN54AC11109FK的Datasheet PDF文件第6页浏览型号SN54AC11109FK的Datasheet PDF文件第7页 
54AC11109, 74AC11109  
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCAS450 – MARCH 1987 – REVISED APRIL 1993  
54AC11109 . . . J PACKAGE  
74AC11109 . . . D OR N PACKAGE  
(TOP VIEW)  
• Flow-Through Architecture Optimizes  
PCB Layout  
• Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
CC  
1PRE  
1Q  
1Q  
GND  
2Q  
2Q  
2PRE  
2CLK  
1CLK  
1K  
1J  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
• EPIC (Enhanced-Performance Implanted  
CMOS) 1-µm Process  
• 500-mA Typical Latch-Up Immunity  
at 125°C  
1CLR  
V
CC  
2CLR  
2J  
2K  
• ESD Protection Exceeds 2000 V,  
MIL STD-883C Method 3015  
• Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
54AC11109 . . . FK PACKAGE  
(TOP VIEW)  
description  
These devices contain two independent J-K  
positive-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs regardless of the levels of the  
other inputs. When preset and clear are inactive  
(high), dataattheJandKinputsmeetingthesetup  
time requirements are transferred to the outputs  
on the positive-going edge of the clock pulse.  
Clocktriggeringoccursatavoltagelevelandisnot  
directly related to the rise time of the clock pulse.  
Following the hold time interval, data at the J and  
K inputs may be changed without affecting the  
levels at the outputs. These versatile flip-flops can  
perform as toggle flip-flops by grounding K and  
tying J high. They also can perform as D-type  
flip-flops by tying the J and K inputs together.  
3
2
1
20 19  
18  
2J  
17 2K  
1K  
1CLK  
NC  
4
5
6
7
8
16  
15  
14  
NC  
2CLK  
2PRE  
1PRE  
1Q  
9 10 11 12 13  
NC – No internal connection  
The 54AC11109 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
74AC11109 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUTS  
PRE  
L
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
CLR  
H
H
L
X
H
†
†
H
L
L
X
H
H
H
↑
L
H
H
H
↑
H
L
L
Toggle  
H
H
↑
H
H
X
Q
Q
0
0
H
H
↑
H
X
H
L
H
H
L
Q
Q
0
0
†
Thisconfigurationisnonstable;thatis, itwillnotpersistwhen  
either PRE or CLR returns to its inactive (high) level.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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