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SN54ABT833JT PDF预览

SN54ABT833JT

更新时间： 2024-11-11 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
9页 156K
描述
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

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SN54ABT833JT 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：unknown风险等级：5.73
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ABT
JESD-30 代码：R-GDIP-T24长度：32.005 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.024 A位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
电源：5 V最大电源电流（ICC）：38 mA
Prop。Delay @ Nom-Sup：5.4 ns传播延迟（tpd）：5.4 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：BICMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
翻译：N/A宽度：7.62 mm
Base Number Matches：1

SN54ABT833JT 数据手册

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SN54ABT833, SN74ABT833  
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS  
SCBS195C – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT833 . . . JT PACKAGE  
SN74ABT833 . . . DW OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OEA  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
High-Drive Outputs (–32-mA I  
,
OH  
64-mA I  
)
OL  
Parity Error Flag With Parity  
Generator/Checker  
ERR 10  
CLR  
15 PARITY  
OEB  
CLK  
11  
12  
14  
13  
Register for Storage of the Parity Error Flag  
GND  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Plastic (NT) and  
Ceramic (JT) DIPs  
SN54ABT833 . . . FK PACKAGE  
(TOP VIEW)  
description  
4
3
2
1
28 27 26  
25  
The ’ABT833 8-bit to 9-bit parity transceivers are  
designedforcommunicationbetweendatabuses.  
When data is transmitted from the A bus to the  
B bus, a parity bit is generated. When data is  
transmitted from the B bus to the A bus with its  
corresponding parity bit, the open-collector  
parity-error (ERR) output indicates whether or not  
an error in the B data has occurred. The  
output-enable (OEA and OEB) inputs can be used  
to disable the device so that the buses are  
effectively isolated. The ’ABT833 provide true  
data at their outputs.  
5
A3  
A4  
A5  
NC  
A6  
A7  
A8  
B3  
B4  
B5  
NC  
B6  
B7  
B8  
6
24  
23  
22  
21  
20  
19  
7
8
9
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
A 9-bit parity generator/checker generates a  
parity-odd (PARITY) output and monitors the  
parity of the I/O ports with the ERR flag. ERR is  
clocked into the register on the rising edge of the  
clock(CLK)input. Theerrorflagregisteriscleared  
with a low pulse on the clear (CLR) input. When  
both OEA and OEB are low, data is transferred  
from the A bus to the B bus and inverted parity is  
generated. Inverted parity is a forced error  
condition that gives the designer more system  
diagnostic capability.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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