5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN54ABT853FK
SN54ABT853FK PDF预览

SN54ABT853FK

更新时间： 2024-11-11 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件信息通信管理
页数 文件大小 规格书
9页 143K
描述
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

阅读下载

中文翻译

获取价格

SN54ABT853FK 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：CERAMIC, LCC-28
针数：28Reach Compliance Code：not_compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.48Is Samacsys：N
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ABT
JESD-30 代码：S-CQCC-N28长度：11.43 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.048 A位数：8
功能数量：1端口数量：2
端子数量：28最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC28,.45SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：38 mA传播延迟（tpd）：6.4 ns
认证状态：Not Qualified座面最大高度：2.03 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：NO LEAD
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：11.43 mmBase Number Matches：1

SN54ABT853FK 数据手册

 浏览型号SN54ABT853FK的Datasheet PDF文件第2页浏览型号SN54ABT853FK的Datasheet PDF文件第3页浏览型号SN54ABT853FK的Datasheet PDF文件第4页浏览型号SN54ABT853FK的Datasheet PDF文件第5页浏览型号SN54ABT853FK的Datasheet PDF文件第6页浏览型号SN54ABT853FK的Datasheet PDF文件第7页 
SN54ABT853, SN74ABT853  
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS  
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997  
SN54ABT853 . . . JT OR W PACKAGE  
SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OEA  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Typical V  
< 1 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 5 V, T = 25°C  
A
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
High-Impedance State During Power Up  
and Power Down  
ERR 10  
15 PARITY  
Parity-Error Flag With Parity  
Generator/Checker  
CLR  
GND  
OEB  
LE  
11  
12  
14  
13  
Latch for Storage of Parity-Error Flag  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Plastic (NT)  
and Ceramic (JT) DIPs  
SN54ABT853 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1
28 27 26  
25  
5
A3  
A4  
A5  
NC  
A6  
A7  
A8  
B3  
B4  
B5  
NC  
B6  
B7  
B8  
6
description  
24  
23  
22  
21  
20  
19  
7
The ’ABT853 8-bit to 9-bit parity transceivers are  
designedforcommunicationbetweendatabuses.  
When data is transmitted from the A bus to the  
B bus, a parity bit is generated. When data is  
transmitted from the B bus to the A bus with its  
corresponding parity bit, the open-collector  
parity-error (ERR) output indicates whether or not  
an error in the B data has occurred. The  
output-enable (OEA and OEB) inputs can be used  
to disable the device so that the buses are  
effectively isolated. The ’ABT853 transceivers  
provide true data at their outputs.  
8
9
10  
11  
12 13 14 15 16 17 18  
NC – No internal connection  
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports  
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the  
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from  
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the  
designer more system diagnostic capability.  
When V  
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

下载PDF

与SN54ABT853FK相关器件

型号 品牌 获取价格 描述 数据表
SN54ABT853FKR TI

获取价格

 		ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CQCC28, CERAMIC, LCC-28
SN54ABT853JT TI

获取价格

 		8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN54ABT853W TI

获取价格

 		8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SN54ABT8543 TI

获取价格

 		SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
SN54ABT8543_15 TI

获取价格

 		SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
SN54ABT8543FK TI

获取价格

 		SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
SN54ABT8543FKR TI

获取价格

 		ABT SERIES, 8-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQCC28
SN54ABT8543JT TI

获取价格

 		SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS
SN54ABT861 TI

获取价格

 		10-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS
SN54ABT861FK TI

获取价格

 		10-BIT TRANSCEIVERS WITH 3-STATE OUTPUTS

与SN54ABT853FK相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证