SN54ABT7819
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SGBS305D – AUGUST 1994 – REVISED APRIL 1998
Member of the Texas Instruments
Widebus Family
Microprocessor Interface Control Logic
Programmable Almost-Full/Almost-Empty
Flag
Advanced BiCMOS Technology
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Fast Access Times of 9 ns With a 50-pF
Load and Simultaneous-Switching Data
Outputs
Read and Write Operations Synchronized
to Independent System Clocks
Released as DSCC SMD (Standard
Microcircuit Drawing) 5962-9470401QXA
and 5962-9470401QYA
Two Separate 512 × 18 Clocked FIFOs
Buffering Data in Opposite Directions
Package Options Include 84-Pin Ceramic
Pin Grid Array (GB) and 84-Pin Ceramic
Quad Flat (HT) Package
IRA and ORA Synchronized to CLKA
IRB and ORB Synchronized to CLKB
HT PACKAGE
(TOP VIEW)
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
AF/AEA
HFA
IRA
AF/AEB
HFB
IRB
1
63
62
61
60
59
58
57
56
55
54
53
52
51
50
2
3
GND
A0
GND
B0
4
5
A1
B1
6
V
V
7
CC
CC
A2
A3
B2
8
B3
9
GND
NC
GND
NC
B4
10
11
12
A4
A5 13
GND 14
A6 15
B5
GND
49 B6
48 B7
A7 16
17
18
19
20
21
47
46
45
44
43
GND
A8
GND
B8
A9
B9
V
V
CC
CC
A10
B10
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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