Si5022/Si5023
PRELIMINARY DATA SHEET
MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMP
Features
High Speed Clock and Data Recovery device with Integrated Limiting Amp:
!
Supports OC-48/12/3, STM-16/4/1,
Gigabit Ethernet, and 2.7 Gbps FEC
DSPLL™ Technology
Low Power—370 mW (TYP)
Small Footprint: 5 mm x 5 mm
Bit-Error-Rate Alarm
! External Reference Not Required
! Jitter Generation 3.0 mUIRMS(TYP)
! Loss-of-signal Level Alarm
! Data Slicing Level Control
! 10 mVPP Differential Sensitivity
!
!
!
!
! 2.5 V (Si5022) or 3.3 V (Si5023) Supply
Ordering Information:
See page 14.
Applications
!
!
!
!
SONET/SDH/ATM Routers
Add/Drop Multiplexers
Digital Cross Connects
Gigabit Ethernet Interfaces
!
SONET/SDH Test Equipment
Optical Transceiver Modules
SONET/SDH Regenerators
Board Level Serial Links
!
!
!
Pin Assignments
Si5022/23
Description
28 27 26 25 24 23 22
The Si5022/23 is a fully integrated, high performance limiting amp and clock and
data recovery (CDR) IC for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1, or
Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also provided
for OC-48/STM-16 applications that employ forward error correction (FEC). An
external reference clock is not required; applications with or without an external
reference clock are supported. Silicon Laboratories’ DSPLL™ technology
eliminates sensitive noise entry points thus making the PLL less susceptible to
board-level interaction and helping to ensure optimal jitter performance.
RATESEL0
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
VDD
1
2
3
4
5
6
7
21
20
19
18
17
16
REXT
RESET/CAL
VDD
GND
Pad
DOUT+
DOUT–
15 TDI
8
9
10 11 12 13 14
The Si5022/23 represents a new standard in low jitter, low power, small size, and
integration for high speed LA/CDRs. It operates from either a 3.3 V (Si5023) or
2.5 V (Si5022) supply over the industrial temperature range (–40°C to 85°C).
Top View
Functional Block Diagram
2
DSQLCH
Squelch
Control
DOUT+
DOUT–
Retimer
BUF
BUF
CLKDSBL
2
CLKOUT+
CLKOUT–
DSPLLTM
2
DIN+
DIN–
Limiting
AMP
Phase-Locked
Loop
LOL
Control
RESET/CAL
2
LOS_LVL
Bias Gen
SLICE_LVL
RATSEL[1:0]
REXT
LTR
LOS
BER_LVL
REFCLK+
REFCLK–
BER_ALM
(Optional)
Preliminary Rev. 0.46 5/01
Copyright © 2001 by Silicon Laboratories
Si5022/23-DS046
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).