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SI5023-X-GM

更新时间: 2024-11-25 03:00:19
品牌 Logo 应用领域
芯科 - SILICON ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路放大器异步传输模式
页数 文件大小 规格书
28页 782K
描述
MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER

SI5023-X-GM 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84应用程序:ATM;SDH;SONET
JESD-30 代码:S-XQCC-N28JESD-609代码:e4
长度:5 mm功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:0.9 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5 mm
Base Number Matches:1

SI5023-X-GM 数据手册

 浏览型号SI5023-X-GM的Datasheet PDF文件第2页浏览型号SI5023-X-GM的Datasheet PDF文件第3页浏览型号SI5023-X-GM的Datasheet PDF文件第4页浏览型号SI5023-X-GM的Datasheet PDF文件第5页浏览型号SI5023-X-GM的Datasheet PDF文件第6页浏览型号SI5023-X-GM的Datasheet PDF文件第7页 
Si5023  
MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER  
Features  
High-speed clock and data recovery device with integrated limiting amp:  
Supports OC-48/12/3, STM-16/4/ Bit error rate alarm  
1, Gigabit Ethernet, and 2.7 Gbps  
FEC  
Reference and referenceless  
operation supported  
®
Loss-of-signal level alarm  
Data slicing level control  
DSPLL technology  
Jitter generation 3.0 mUI  
rms  
10 mV differential sensitivity  
(TYP)  
PP  
Ordering Information:  
Small footprint: 5 x 5 mm  
3.3 V supply  
See page 25.  
Applications  
SONET/SDH/ATM routers  
Add/drop multiplexers  
Digital cross connects  
Gigabit Ethernet interfaces  
SONET/SDH test equipment  
Optical transceiver modules  
SONET/SDH regenerators  
Board level serial links  
Pin Assignments  
Si5023  
28 27 26 25 24 23 22  
Description  
RATESEL0  
RATESEL1  
LOS_LVL  
SLICE_LVL  
REFCLK+  
REFCLK–  
LOL  
VDD  
1
2
3
4
5
6
7
21  
20  
19  
18  
17  
16  
15  
REXT  
The Si5023 is a fully-integrated, high-performance limiting amp and clock  
and data recovery (CDR) IC for high-speed serial communication systems.  
It derives timing information and data from a serial input at OC-48/12/3,  
STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data  
streams is also provided for OC-48/STM-16 applications that employ  
forward error correction (FEC). Use of an external reference clock is  
RESET/CAL  
VDD  
GND  
Pad  
DOUT+  
DOUT–  
GND  
8
9
10 11 12 13 14  
®
optional. Silicon Laboratories DSPLL technology eliminates sensitive  
noise entry points, thus making the PLL less susceptible to board-level  
interaction and helping to ensure optimal jitter performance.  
Top View  
The Si5023 represents a new standard in low jitter, low power, small size,  
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply  
over the industrial temperature range (–40 to 85 °C).  
Functional Block Diagram  
LOS_LVL  
Signal  
Detect  
DSQLCH  
LOS  
2
DOUT+  
DOUT–  
Retimer  
BUF  
BUF  
2
DIN+  
DIN–  
Limiting  
Amp  
DSPLL  
BER  
Monitor  
2
CLKOUT+  
CLKOUT–  
CLK_DSBL  
REFCLK+  
REFCLK–  
(Optional)  
2
Lock  
Detection  
2
Reset/  
Calibration  
Bias Gen.  
REXT  
BER_ALM  
RESET/CAL  
BERMON  
BER_LVL  
RATESEL  
SLICE_LVL  
LOL  
LTR  
Rev. 1.25 10/05  
Copyright © 2005 by Silicon Laboratories  
Si5023  

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