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SI5040

更新时间: 2024-10-04 03:32:07
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
2页 131K
描述
10 Gbps XFP Transceiver

SI5040 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.72光纤设备类型:TRANSCEIVER
安装特点:SURFACE MOUNT最高工作温度:85 °C
最低工作温度:-40 °C子类别:Fiber Optic Transceivers
最大供电电压:1.8 V表面贴装:YES
Base Number Matches:1

SI5040 数据手册

 浏览型号SI5040的Datasheet PDF文件第2页 
Si5040  
10 Gbps XFP Transceiver  
Description  
Summary of Key Features  
- Continuous operation from 9.95 to 11.4 Gbps  
The Si5040 is a high performance, protocol agnostic  
10 Gbps XFP transceiver featuring integrated jitter  
attenuating capability based on Silicon Laboratories’ proven  
DSPLL technology. The device is designed to perform  
reshaping, re-amplifying, and retiming of the bi-directional  
10 Gbps serial data by integrating two independent Clock  
and Data Recoveries (CDRs), two DSPLL-based Clock  
Multiplier Units (CMUs), and data re-timers in both transmit  
and receive directions. The DSPLL-based CMU and the  
data re-timer in the transmit direction eliminate the need for  
external jitter clean up circuitry to achieve compliance with  
telecom and datacom jitter specifications. The same DSPLL  
technology minimizes jitter in the receive path ensuring  
error free operation with ASICs or FPGAs connected via  
the XFI interface. The Si5040 provides three receive signal  
quality monitors including analog loss-of-signal (LOS)  
detection, consecutive identical digit (CID) detection, and a  
proprietary digital measure of receive eye opening.  
Comprehensive diagnostics are also supported via two loop  
back modes as well as pattern generation and check  
capability on both the receive and transmit data paths. The  
Si5040 provides industry leading jitter performance for all  
telecom and datacom protocols between 9.9 and  
11.4 Gbps, including OC-192/STM-64, 10 GbE, 10 G Fiber  
Channel, and their associated forward error correction  
(FEC) data rates:  
- Transmit jitter attenuation with selectable loop  
bandwidths from 200 Hz to 1.2 MHz  
- SONET jitter generation 2.5 mUI RMS  
- SONET jitter tolerance > 0.55UIpp (0.15UIpp spec)  
- Integrated limiting amplifier with high input sensitivity:  
5 mV ppd Typ  
- Auto-slice adjustment (programmable adjust optional)  
- Programmable sample phase adjust  
- Three signal quality monitors: loss-of-signal (LOS)  
detector, consecutive identical digit (CID) detector, and a  
receive eye opening monitor  
- PRBS or user-defined pattern generation and checking  
in both TX and RX directions  
- Operation over wide power supply variation  
(–10% to +5%)  
- Industrial temperature operation (–40 to +85 °C)  
- Adjustable output swing  
- Low power: 575 mW (typ)  
- Small size: 5 x 5 mm LGA  
- Serial microcontroller interface  
Applications  
- XFP Optical Module  
- Line card and Backplane  
- Regenerate 10 Gbps electrical signal for longer  
- OC192/STM64: 9.95 Gbps  
reach of the PCB trace  
- 10 Gbps Ethernet LAN PHY: 10.3125 Gbps  
- 10 Gbps Fibre Channel: 10.51875 Gbps  
- G.709 OTU2: 10.709 Gbps  
- Added jitter attenuation with jitter transfer  
compliance  
- Added jitter tolerance  
- CWDM  
- 10 Gbps Ethernet + FEC: 11.0957 Gbps  
- 10 Gbps Fibre Channel + FEC: 11.3176 Gbps  
- Complete regeneration of the 10 Gbps signal in  
O/E/O applications  
- Optical Test Equipment  
To address XFP module space and power constraints, the  
Si5040 comes in a 5 x 5 mm LGA package and only  
consumes 575 mW typ.  
- 10 Gbps Standalone Clock and Data Recovery  
- 10 Gbps Standalone Optical Transmitter  
RX_LOS  
RX_LOL  
Optical Line  
Side  
XFI System  
Side  
Phase  
Adjust  
RX Pattern  
Check  
RX Pattern  
Gen  
RXDIN  
LA  
FIFO &  
ReTimer  
CDR  
Clk  
D
CML  
RD  
Slice  
Adjust  
Alarms  
Interrupt  
DSPLL®  
Jitter Attenuator  
µController  
Interface  
XFI Loopback  
Line Loopback  
Optional  
Crystal  
Serial Port  
(I2C or 3-wire)  
DSPLL®  
Jitter Attenuator  
RefCLK  
(optional)  
Clk  
FIFO &  
ReTimer  
D
CDR  
Equalizer  
TD  
TXDOUT  
CML  
TX Pattern  
Gen  
TX Pattern  
Check  
Networking Products  
Copyright © 2006 by Silicon Laboratories  
1.5.2006  

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