Si5040
10 Gbps XFP TRANSCEIVER WITH JITTER ATTENUATOR
Features
Complete, high-performance, low-power, 10 Gbps XFP transceiver featuring
independent CDRs, DSPLL®-based jitter-attenuating CMUs, and data retimers in both
Si5100
transmit and receive directions.
Transmitter jitter generation 2.5 mUIrms
(typical)
DSPLL-based, jitter-attenuating CMUs
in both transmit and receive directions
Frequency-agile jitter filtering from 9.8 to
11.35 Gbps (continuous)
Compliant to XFP specifications and
jitter specifications for telecom
Automatic slicing level adjustment with
optional programmable override
Programmable sample phase
adjustment
Line loopback, XFI loopback, pattern
generation, and pattern check test
capabilities
1.8/3.3 V or single 1.8 V supply
575 mW (typ) power dissipation
5x5 mm LGA package
(SONET/SDH, OTU-2) and datacom
(10 GbE/10 GbE+FEC and
Ordering Information:
10 GFC/10 GFC+FEC) applications
Supports referenceless operation
Integrated limiting amplifier provides
better than 8 mV receiver sensitivity
User-programmable receiver loss-of-
signal (LOS) detector
See page 103.
Serial microcontroller interface control
Pin Assignments
Applications
Si5040
(Transparent Top View)
XFP telecom modules
XFP datacom modules
Optical test equipment
Jitter-attenuation and signal
regeneration of 10 Gbps serial signal
on line cards
32 31
30 29 28 27 26 25
GND
1
2
3
4
5
6
7
8
24 SCK
23 GND
Description
RX_LOL
RX_LOS
GND
PAD
GND
PAD
22
TD+
The Si5040 is a complete, low-power, high-performance XFP transceiver suitable for
multiple XFP module types, from short-reach datacom to long-reach telecom
applications. The Si5040 integrates a rate-agile, programmable-bandwidth, jitter-
attenuating CMU in the transmit direction, which significantly attenuates jitter present at
the XFI interface and on the applied reference clock, removing the need for an external
jitter cleanup circuit. The device supports referenceless operation or operation with a
synchronous or asynchronous reference clock. The device can be completely configured
through a serial microcontroller interface. The Si5040 is compliant with all XFP
requirements in both datacom and telecom applications. The Si5040 is packaged in a
5x5 mm LGA package and dissipates 575 mW (typ).
21 TD–
20 GND
19 RD+
VDDIO
GND
GND
PAD
GND
PAD
RXDIN–
RXDIN+
GND
18
RD–
17 GND
9
10 11 12 13 14 15 16
Functional Block Diagram
RX_LOL
RX_LOS
LA
Program
mable
Equalizer
D
CDR
Clk
CML
RXDIN
RD
FIFO
Interrupt
DSPLLTM
Control
Jitter Attenuator
XFI
Loopback
Line
Loopback
RefCLK
(optional)
DSPLLTM
Jitter Attenuator
Serial
Port
Serial
Interface
Clk
D
CDR
Equalizer
TXDOUT
CML
TD
FIFO
Rev. 1.3 6/12
Copyright © 2012 by Silicon Laboratories
Si5040