Datasheet > SI5100

SI5100

更新时间： 2024-10-04 03:32:07

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
40页	498K
描述
SiPHY⑩ OC-48/STM-16 SONET/SDH TRANSCEIVER

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SI5100 数据手册

Si5100

SiPHY™ OC-48/STM-16 SONET/SDH TRANSCEIVER

Features

Complete, low-power, high-speed, SONET/SDH transceiver with

integrated limiting amp, CDR, CMU, and MUX/DEMUX

Si5100

ꢀ Data rates supported:

OC-48/STM-16 through 2.7 Gbps

FEC

ꢀ SONET-compliant loop timed

operation

ꢀ Programmable slicing level and

ꢀ Low-power operation 1.2 W (typ)

sample phase adjustment

ꢀ DSPLL™ based clock multiplier ꢀ LVDS/LVPECL compatible

unit w/ selectable loop filter

bandwidths

interface

ꢀ Single supply 1.8 V operation

ꢀ 15 x 15 mm BGA package

Bottom View

ꢀ Integrated limiting amplifier

ꢀ Loss-of-signal (LOS) alarm

ꢀ Diagnostic and line loopbacks

Ordering Information:

See page 35.

Applications

ꢀ SONET/SDH transmission

ꢀ Optical transceiver modules

ꢀ SONET/SDH test equipment

systems

Description

The Si5100 is

a complete low-power transceiver for high-speed serial

communication systems operating between OC-48 and 2.7 Gbps. The receive

path consists of a fully-integrated limiting amplifier, clock and data recovery unit

(CDR), and 1:16 deserializer. The transmit path combines a low-jitter clock

multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories’

DSPLL technology to provide superior jitter performance while reducing design

complexity by eliminating external loop filter components. To simplify BER

optimization in long-haul applications, programmable slicing and sample phase

adjustment are supported. The Si5100 operates from a single 1.8 V supply over

the industrial temperature range (–20 to 85 °C).

Functional Block Diagram

SLICELVL

PHASEADJ

RXDOUT[15:0]

Limiting

AMP

RXDIN

CDR

Diagnostic

Loopback

Line

RXCLK

Loopback

TXDOUT

TXDIN[15:0]

DSPLL^TM

TX CM U

TXCLKOUT

TXCLK16IN

REFCLK

BWSEL[1:0]

Rev. 1.1 7/04

Si5100

12 3 4 5 6 7...40

中文翻译

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