ACS8944 JAM PLL
Jitter Attenuating, Multiplying Phase Locked Loop
for OC-12/STM-4
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Introduction
Features
The ACS8944 JAM PLL is a Jitter- Attenuating, Multiplying
Phase-Locked Loop, for generating low jitter output clocks
compliant up to SONET OC-12 and STM-4 622.08 MHz
specifications. Its primary function is to clean up clock
jitter for high performance optical line cards which have
OC-3 or OC-12 SONET serializers or framers, and is the
entry level device in Semtech’s range of JAM PLLs.
Meets rms jitter requirements of:
Telcordia GR-253-CORE[8] for OC-3 and OC-12
ITU-T G.813[4]/G.812[3] for STM-1 and STM-4 rates
ETSI EN300-462-7[1]/EN302-084[2] up to STM-16
rates
Typical jitter generation down to:
The ACS8944 JAM PLL has a single differential LVPECL
input and a single differential LVPECL output. Both input
and output clock frequencies are individually
programmable and can be hardware configured to be any
of 19.44 MHz, 38.88 MHz, 77.76 MHz or 155.52 MHz.
• 0.3 ps rms for 250 kHz to 5 MHz band for G.813,
or EN300-462, at STM-4 (OC-12) rates
• 2.8 ps rms for 12 kHz to 20 MHz band (against
4.02 ps rms for GR-253-CORE at OC-48 rate)
The headline jitter figures quoted for the ACS8944
depend on the frequency band over which the jitter is
measured. For example, typical stand-alone output jitter
is typically 2.8 ps rms (well within GR-253-CORE[8]
specification requirements of 16.1 ps rms for OC-12 and
64.3 ps rms for OC-3).
Pull-in range ±400 ppm about center input frequency
Frequency translation e.g. 19.44 MHz to 155.52 MHz
3.3 V operation, - 40 to +85°C temperature range
Small outline leadless 7 mm x 7 mm QFN48 package
Demonstration Board available on request
PLL bandwidth and jitter peaking are fully adjustable.
The device's operating bandwidth (and consequently the
jitter attenuation point relating to this bandwidth) is set by
external passive components in a differential
Supports bandwidths from 2 kHz for superior input
jitter filtering
arrangement which offers good noise immunity.
Lead (Pb)-free version available (ACS8944T), RoHS[9]
and WEEE[10] compliant
[1],[2], etc.
Note...For items marked
references are given in full
Block Diagram
in the Reference Section on page 21.
Figure 1 Simplified Block Diagram of the ACS8944 JAM PLL
Loop
Filter
RESETB
VC
Differential
Input Reference
LVPECL
Differential
Clock Output
LVPECL
PFD
Charge
Pump
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
Frequency
Divider
2.5 GHz
VCO
Frequency
Divider
LVPECL
LVPECL
Control and Monitor
F8944D_001Blockdiag_02
Revision 3/November 2006 © Semtech Corp.
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