Datasheet > ACS8947T

ACS8947T

更新时间： 2024-02-12 22:54:59

品牌	Logo	应用领域
商升特 - SEMTECH		/
页数	文件大小	规格书
30页	1882K
描述
Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path

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ACS8947T 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	7 X 7 MM, LEAD FREE, QFN-48	针数：	48
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.81	应用程序：	SONET;SDH
JESD-30 代码：	S-XQCC-N48	JESD-609代码：	e3
长度：	7 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	Base Number Matches：	1

ACS8947T 数据手册

ACS8947T JAM PLL

Jitter Attenuating, Multiplying Phase-Locked Loop with

Automatic Input Switch and Data Resynchronization Path

UNICATIONS

ADVANCED COMMS & SENSING

Introduction

FINAL

Features

DATASHEET

The ACS8947T JAM PLL is a general pupose, Integer N,

jitter-attenuating, differential phase-locked loop for

generating low jitter output clocks. Frequency translation,

reference switching between clock inputs and

resynchronization features are provided also. Typical

application areas include Ethernet, SONET/SDH, PCI, 3G

and wireless systems.

Z Highly configurable high performance Integer N PLL

with integrated VCO.

Z VCO frequency range 2.35 GHz to 2.9 GHz.

Z Configurable closed loop bandwidth from 2 kHz

upwards.

Z PLL fully configured by hardwired configuration matrix:

Typical output jitter generation in a SONET/SDH OC-12

system is 2.8 ps RMS, making the ACS8947T an ideal

dejittering solution for use with Semtech clock and line

card parts ACS8510, ACS8520, ACS8525, ACS8522,

ACS8530 and ACS9510.

no requirement for an external microprocessor.

Z Full control over internal dividers allows the device to

be configured for a wide range of frequency

translation and jitter cleaning applications.

Z Meets RMS jitter requirements for OC3 and OC12

The ACS8947T has two differential frequency-

programmable LVPECL reference inputs and one

differential synchronization input. The device is capable of

locking across a wide input frequency range of 580 kHz to

180 MHz. Four independently-supplied differential

outputs are available, programmable as LVPECL or CML.

Each output supports a maximum output frequency rate

of up to 625 MHz. All device settings are fully hardwire

configured. An external microprocessor is not required to

program the PLL.

telecommunications systems.

Z Wide input frequency range of 580 kHz to 180 MHz.

Z Wide output frequency range of 1.23 MHz to

625 MHz.

Z Input activity monitors and lock detector.

Z Automatic or manual control of reference selection.

Z External feedback option.

Z Wide tracking range of 200 ppm.

Z Powerful evaluation board and GUI tool for

configuration and device assessment.

Z 3.3 V operation: temperature range - 40°C to +85°C.

Z Small outline, leadless, 7 mm x 7 mm QFN48

Block Diagram

package.

Figure 1 Simplified Block Diagram of the ACS8947T JAM PLL

Page1

www.semtech.com

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