®
ToPSync
ACS9520T
ADVANCED COMMS PRODUCT GROUP
PRODUCT BRIEF
About the ToPSync® ACS9520T
Features
PTP timing features
This is the product brief for the ToPSync® ASSP ACS9520T. The
datasheet should be read in conjunction with the ACS9520T
user guide, API documentation and other information available
.
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PTP Grandmaster selection - automatic or manual PTP
master/slave mode selection.
at the ToPSync® Resource Center.
Powerful network delay analysis - full time-alignment in the
slave over hostile networks (Layer 2 or layer 3 networks).
Dynamic adaptation - to network delay variations. Network
loading change tolerant (e.g., ramps and steps).
Time alignment - better than ±1 μs on a managed
10-switch GbE network under G.8261 test conditions.*
Frequency alignment - better than ±10 ppb on a managed
5-switch GbE network under G.8261 test conditions.*
There are many applications in which it is necessary to lock a
remote clock signal to a central frequency source, and there
are other applications which require the alignment of a clock
to a central source of time. The ACS9520T combines
Semtech's synchronous equipment timing source (SETS)
functionality and ToPSync® technology and can therefore be
used for both applications. In this datasheet, the words SETS
and TDM Block are synonymous, and both terms are used.
TDM timing features
SETS functionality is used for frequency-locking applications in
.
Programmable TDM timing bandwidth - for wander and
jitter tracking/attenuation, 0.1 Hz to 70 Hz in 10 steps.
Automatic hit-less source switchover - on loss of input.
Output clock phase adjustment - in 6 ps steps to ±200 ns.
SDH/SONET and Ethernet equipment. ToPSync® technology
combines the IEEE 1588 v2 protocol with Semtech's patented
packet delay filtering algorithms, which allow a reference clock
to be transported across a packet switched network without
special adaptations of switches or routers in the network. It is
ideal for carrying timing across a legacy packet switched
network.
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Device features
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Fully integrated - Integrates hardware precision
timestamping with on-the-fly insertion. Powerful integrated
processor and clock recovery algorithm.
IEEE 1588 is often known as precision time protocol (PTP), the
acronym that is generally used in this document.
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ECC - Provision for optional ECC memory.
Ultra low noise clock generation - Interface to the Semtech
SX1790 Ultra low noise frequency synthesizer.
Timing synchronization on a chip - supporting transitions
from legacy circuit networks to new packet technology.
Suitable applications - Stratum 3, 3E, 4E, 4, SONET
Minimum Clock (SMC) or SONET/SDH Equipment Clock
(SEC) or Ethernet, IEEE1588 PTP and Synchronous
Ethernet.
The ACS9520T supports:
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Timebase derived from:
PTP slave, SONET/SDH recovered clock, BITS/SSU input,
SyncE recovered clock, GPS, 1PPS, precision holdover.
Physical layer clock sources are jitter and wander
attenuated according to G.813, G.823, GR1244, GR253,
G.8261, G.8262(draft) etc.
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Clocks - 9 clock inputs and 5 clock outputs.
Precision holdover - in all modes.
Ports - 2 x SGMII, SDRAM, serial interface and JTAG.
Time-of-day - PPnS top-of-second signal plus
current-time-since-epoch message on a UART.
Output characteristics:
Technology bridging:
Derive timing from one input technology (SONET, SDH,
SyncE, PTP) and provide timing to all output technologies
simultaneously.
PTP Grandmaster:
PTP Grandmaster functions provided based on the
timebase including support for UTC, TAI, GPS time epochs.
PTP Slave:
Multi-hop locking (ordinary clock) or interworking with
boundary clocks or transparent clocks with sophisticated
packet delay filters and adaptation algorithms.
TDM/clocks:
.
Time-aligned output pair:
1 PPS and 125 MHz divided by n (n = 4 to 125000).
Frequency-aligned outputs:
1 Hz and programmable frequency 1 kHz to 180 MHz.
Low jitter frequency-aligned outputs:
SONET and SDH OC-n rates: 3.84 MHz to 155.52 MHz.
Includes all Semtech SETS family functions for physical
layer input and output synchronization.
SyncE rates: 25 MHz, 50 MHz, 62.5 MHz and 125 MHz
Local oscillator: ±20 ppm or better.
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SyncE:
BGA package: 256 pin, 14 mm x 14 mm.
Lead-free - RoHS and WEEE compliant.
Integrates Semtech eSETS technology for the physical layer
input and output synchronization of ethernet PHY devices.
Self test - in which the device self-checks for consistency,
checks the external SDRAM for faults, and performs
rudimentary checks of the external Ethernet PHYs.
A simplified system diagram is shown in Figure 1.
*
This is an indication of Semtech tested performance and is not
guaranteed across all types of switches and network conditions.
Please contact Semtech ToPSync® support for further details.
ACS9520TPB_US, Revision 01, 2nd November 2012
©2012 Semtech Corp.
Page 1
www.semtech.com
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