Datasheet > S3012A

S3012A

更新时间： 2024-09-17 19:44:43

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		/
页数	文件大小	规格书
21页	136K
描述
Receiver, 1-Func, PQFP80, PLASTIC, QFP-80

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技术参数
数据手册

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S3012A 技术参数

生命周期：	Contact Manufacturer	包装说明：	QFP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	Is Samacsys：	N
JESD-30 代码：	S-PQFP-G80	长度：	14 mm
功能数量：	1	端子数量：	80
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	SQUARE	封装形式：	FLATPACK
座面最大高度：	2.8 mm	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH RECEIVER
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

S3012A 数据手册

DEVICE SPECIFICATION

S3011/S3012

SONET/SDH/ATM OC-3 TRANSMITTER AND RECEIVER

BiCMOS PECL CL

K GENERATOR

GENERAL DESCRIPTION

FEATURES

• Complies with ANSI, Bellcore, and ITU-T

specifications

The S3011/S3012 SONET/SDH transmitter and re-

ceiver chips are fully integrated serialization/

deserialization SONET OC-3 (155.52 Mbit/s) interface

devices. With architecture developed by the Pacific

Microelectronics Centre (PMC), the chipset performs

allnecessaryserial-to-parallelandparallel-to-serialfunc-

tions in conformance with SONET/SDH transmission

standards. The devices are also suitable for ATM appli-

cations. Figure 1 shows a typical network application.

• On-chip high-frequency PLL for clock

generation and clock recovery

• Supports 155.52 Mbit/s (OC-3)

• Reference frequency of 19.44 MHz

• Interface to both PECL and TTL/CMOS logic

• 8-bit TTL/CMOS datapath

• Compact 80 PQFP package

• Diagnostic loopback mode

• Lock detect

On-chip clock synthesis is performed by the high-

frequency phase-locked loop on the S3011 transmitter

chip allowing the use of a slower external transmit clock

reference. Clock recovery is performed on the S3012

receiver chip by synchronizing its on-chip VCO directly

to the incoming data stream. The S3012 also performs

SONET/SDH frame detection. The chipset can be used

with 19.44 MHz reference clocks, in support of existing

system clocking schemes.

• Low jitter PECL interface

• < 2.5 Watt per set

APPLICATIONS

• SONET/SDH-based transmission systems

• SONET/SDH modules

• SONET/SDH test equipment

• ATM over SONET

• Section repeaters

• Add drop multiplexors

• Broad-band cross-connects

• Fiber optic terminators

• Fiber optic test equipment

The low jitter PECL interface guarantees compliance

with the bit-error rate requirements of the Bellcore,

ANSI, and ITU-T standards. The S3011/S3012 chipset

is packaged in a 80 PQFP, offering designers a small

package outline.

Figure 1. System Block Diagram

S3011

SONET/SDH

Transmitter

Network

Interface

Processor

Network

Interface

Processor

S3012

SONET/SDH

Receiver

OTX

ORX

12 3 4 5 6 7...21

中文翻译

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与S3012A相关器件

型号	品牌	获取价格	描述	数据表
S3014A-1	ROCHESTER	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014A-1	AMCC	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014A-6	AMCC	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014A-6	ROCHESTER	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014D-1	ROCHESTER	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014D-1	AMCC	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014D-6	AMCC	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014PH	STMICROELECTRONICS	获取价格	30A, 1000V, SCR, TO-220AB
S3014VH	STMICROELECTRONICS	获取价格	30A, 1200V, SCR, TO-220AB
S3015AH0	AMCC	获取价格	ATM Network Interface, 1-Func, PDSO52, PQFP, TEP, 52 PIN

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