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S3019A PDF预览

S3019A

更新时间: 2024-09-23 20:05:39
品牌 Logo 应用领域
AMCC ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
22页 149K
描述
Transceiver, 1-Func, PQFP80, 14 MM, PLASTIC, QFP-80

S3019A 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP, QFP80,.7SQ针数:80
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.77应用程序:ATM;SDH;SONET
JESD-30 代码:S-PQFP-G80长度:14 mm
功能数量:1端子数量:80
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP80,.7SQ封装形状:SQUARE
封装形式:FLATPACK电源:3.3 V
认证状态:Not Qualified座面最大高度:2.8 mm
子类别:ATM/SONET/SDH ICs标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH TRANSCEIVER
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

S3019A 数据手册

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®
DEVICE  
SPECIFICATION  
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR  
S3019  
FEATURES  
GENERAL DESCRIPTION  
• Complies with Bellcore and ITU-T  
specifications  
• On-chip high-frequency PLLs for clock  
generation and clock recovery  
• Supports 155.52 Mbps (OC-3) and 622.08  
Mbps (OC-12)  
• Selectable reference frequencies of 19.44,  
38.88, 51.84 or 77.76 MHz  
• Interface to both LVPECL and TTL logic  
• Simple interface with 3.3 V or 5 V Optical  
modules  
• Directly compatible with 3.3 V or 5 V network  
interface devices  
• 8-bit TTL data path  
• Compact 14 mm 80 PQFP package  
• Diagnostic loopback mode  
• Lock detect  
• Low jitter LVPECL interface  
• Single 3.3 V supply  
The S3019 SONET/SDH transceiver chip is a fully  
integrated serialization/deserialization SONET OC-12  
(622.08 Mbit/s) and OC-3 (155.52 Mbps) interface de-  
vice. The chip performs all necessary serial-to-parallel  
and parallel-to-serial functions in conformance with  
SONET/SDH transmission standards. The device is  
suitable for SONET-based ATM applications. Figure  
1 shows a typical network application.  
On-chip clock synthesis is performed by the high-  
frequency phase-locked loop on the S3019  
transceiver chip allowing the use of a slower external  
transmit clock reference. Clock recovery is performed  
on the device by synchronizing its on-chip VCO directly  
to the incoming data stream. The S3019 also per-  
forms SONET/SDH frame detection. The chip can be  
used with a 19.44, 38.88, 51.84 or 77.76 MHz refer-  
ence clock, in support of existing system clocking  
schemes.  
The low jitter LVPECL interface guarantees compliance  
with the bit-error rate requirements of the Bellcore  
and ITU-T standards. The S3019 is packaged in a  
14 mm 80 PQFP, offering designers a small package  
outline.  
APPLICATIONS  
• SONET/SDH-based transmission systems  
• SONET/SDH modules  
• SONET/SDH test equipment  
• ATM over SONET/SDH  
• Section repeaters  
• Add Drop Multiplexers (ADM)  
• Broad-band cross-connects  
• Fiber optic terminators  
• Fiber optic test equipment  
Figure 1. System Block Diagram  
8
8
OTX  
ORX  
S3019  
SONET/SDH  
Transceiver  
Network  
Interface  
Processor  
Network  
Interface  
Processor  
S3019  
SONET/SDH  
Transceiver  
8
8
OTX  
ORX  
1
April 12, 2000 / Revision F  

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