Datasheet > S3014A-1

S3014A-1

更新时间： 2024-11-07 19:48:15

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
10页	99K
描述
Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44

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中文翻译

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技术参数
数据手册

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S3014A-1 技术参数

生命周期：	Contact Manufacturer	包装说明：	QCCJ,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PQCC-J44
长度：	16.484 mm	负电源额定电压：	-5.2 V
功能数量：	1	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
座面最大高度：	4.4958 mm	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
温度等级：	INDUSTRIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	16.484 mm	Base Number Matches：	1

S3014A-1 数据手册

DEVICE SPECIFICATION

S3014

SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT

BiCMOS PECL CLOCK GENERATOR

SONET/SDH CLOCK RECOVERY AND SYNTHESIS UNIT

S3014

GENERAL DESCRIPTION

FEATURES

• Complies with ANSI, Bellcore, and CCITT

specifications for jitter tolerance

• On-chip high frequency PLL with internal loop

filter for clock generation or clock recovery

• Supports clock generation for STS-3/STM-1

(155.52 MHz)

• Supports clock recovery for STS-3/STM-1

(155.52 Mbit/s) or STS-12/STM-4

(622.08 Mbit/s) NRZ data

• Selectable 19.44 MHz, 51.84 MHz, or

155.52 MHz reference frequency

• Lock detect—monitors transition density

and run length

The function of the S3014 clock synthesis and recov-

ery unit is to derive high speed timing signals for

SONET/SDH-based equipment. The S3014 is imple-

mented using AMCC’s proven Phase Locked Loop

(PLL) technology.

In Clock Recovery mode, the S3014 receives either

an STS-3/STM-1 or STS-12/STM-4 scrambled NRZ

signal and recovers the clock from the data. The chip

outputs a differential ECL bit clock and retimed data.

In Clock Synthesis mode, the S3014 receives a

19.44, 51.84, or 155.52 MHz reference clock and out-

puts an STS-3/STM-1 or STS-12/STM-4 differential

ECL clock.

• Low power

• Low-jitter ECL interface

• Small 44 PLCC or CLCC package

• TTL reference clock output

The S3014 utilizes an on-chip PLL which consists of

a phase detector, a loop filter, and a voltage con-

trolled oscillator (VCO). The phase detector

compares the phase relationship between the VCO

output and the REFCLK input, a loop filter converts

the phase detector output into a smooth DC voltage,

and the DC voltage is input to the VCO whose fre-

quency is varied by this voltage. A block diagram is

shown in Figure 1.

Figure 1. System Block Diagram

CAP1

LOOP

VCO

FILTER

CAP2

REFCKINP/N

TSTCLKEN

SEL(2:0)

REFCKOUT

SERCLKOP/N

CLOCK

DIVIDER

LOCK

DETECTOR

LOCKDET

RST

PHASE DETECTOR

SERDATOP/N

LOS

SERDATIP/N

12 3 4 5 6 7...10

中文翻译

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与S3014A-1相关器件

型号	品牌	获取价格	描述	数据表
S3014A-6	AMCC	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014A-6	ROCHESTER	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014D-1	ROCHESTER	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014D-1	AMCC	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014D-6	AMCC	获取价格	Clock Recovery Circuit, 1-Func, PQCC44, PLASTIC, LCC-44
S3014PH	STMICROELECTRONICS	获取价格	30A, 1000V, SCR, TO-220AB
S3014VH	STMICROELECTRONICS	获取价格	30A, 1200V, SCR, TO-220AB
S3015AH0	AMCC	获取价格	ATM Network Interface, 1-Func, PDSO52, PQFP, TEP, 52 PIN
S3016A	AMCC	获取价格	ATM Network Interface, 1-Func, PQFP52, HEAT SINK, PLASTIC, TQFP-52
S3016AH0	AMCC	获取价格	ATM Network Interface, 1-Func, PDSO52, PQFP, TEP, 52 PIN

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