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S3016A PDF预览

S3016A

更新时间: 2024-02-06 07:54:31
品牌 Logo 应用领域
AMCC ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
23页 148K
描述
ATM Network Interface, 1-Func, PQFP52, HEAT SINK, PLASTIC, TQFP-52

S3016A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:HQFP, QFP52,.47SQ
针数:52Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.78
应用程序:ATM;SONET运营商类型:E-4
运营商类型(2):STS-3/OC-3数据速率:155520 Mbps
JESD-30 代码:S-PQFP-G52JESD-609代码:e0
长度:10 mm功能数量:1
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HQFP封装等效代码:QFP52,.47SQ
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified子类别:Digital Transmission Interfaces
最大压摆率:240 mA标称供电电压:5 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH NETWORK INTERFACE
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

S3016A 数据手册

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®
DEVICE SPECIFICATION  
S3015/S3016  
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS  
FEATURES  
GENERAL DESCRIPTION  
• Complies with ANSI, Bellcore, and ITU-T  
specifications  
• On-chip high-frequency PLL for clock  
generation and clock recovery  
• On-chip analog circuitry for transformer driver  
and equalization  
The S3015 transmitter and S3016 receiver derive high  
speed timing signals for SONET/SDH or PDH–based  
equipment. These circuits are implemented using  
AMCC’s proven Phase Locked Loop (PLL) technology.  
Figures 1a and 1b show typical network applications.  
The S3015 and S3016 each have an on-chip VCO  
whichcanbesynchronizeddirectlytotheincomingdata  
stream. The chipset can be used with a 19.44 MHz  
referenceclockwhenoperatedintheSONET/SDHOC-  
3 mode. In E4 mode the chipset can be operated with a  
17.408 MHz reference clock in support of existing  
system clocking schemes. On-chip coded-mark-inver-  
sion (CMI) encoding and decoding is provided for  
139.264 Mbit/s and 155.52 Mbit/s interfaces.  
• Supports 139.264 Mbit/s (E4) and 155.52 Mbit/s  
(OC-3) transmission rates  
• Supports 139.264 Mbit/s and 155.52 Mbit/s  
Coded Mark Inversion (CMI) interfaces  
• Reference frequencies of 19.44 (OC-3) or  
17.408 MHz (E4)  
• Interface to both PECL and TTL logic  
• Lock detect on clock recovery device  
• Low jitter PECL interface  
• 1.6W total typ power  
• +5V only power supply  
• Small 52 PQFP TEP package  
• Supports both electrical and optical interfaces  
The low jitter PECL interface guarantees compliance  
with the bit-error rate requirements of the Bellcore,  
ANSI, and ITU-T standards. The S3015/S3016 chipset  
is packaged in a .65mm pitch, compact 52-pin PQFP,  
offering designers a small package outline.  
APPLICATIONS  
The S3015 and S3016 provide the major components  
on-chip for a coaxial cable interface, including analog  
transformer driver circuitry and equalization interface  
circuitry.  
ATM over SONET  
OC-3/STM-1 or E4-based transmission systems  
OC-3/STM-1 or E4 modules  
OC-3/STM-1 or E4 test equipment  
Section repeaters  
Add drop multiplexors  
Broadband cross-connects  
• Fiber optic terminators  
• Fiber optic test equipment  
Figure 1a. Electrical Interface  
COAX  
139/155 Mb/s NRZ  
139/155 Mb/s CMI  
139/155 Mb/s CMI  
S3015  
S3016  
E4/STM-1/OC-3  
OVERHEAD  
PROCESSOR  
XFMR  
XFMR  
139/155 Mb/s NRZ  
17.408/19.44 Mhz  
COAX  
OSC  
Figure 1b. Optical Interface  
155 Mb/s NRZ  
E4/STM-1/OC-3  
OTX  
OVERHEAD  
PROCESSOR  
155 Mb/s NRZ  
155 MHz  
155 Mb/s NRZ  
ORX  
S3015  
S3016  
OSC  
1

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