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S3016A PDF预览

S3016A

更新时间: 2024-02-07 14:05:36
品牌 Logo 应用领域
AMCC ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
23页 148K
描述
ATM Network Interface, 1-Func, PQFP52, HEAT SINK, PLASTIC, TQFP-52

S3016A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:HQFP, QFP52,.47SQ
针数:52Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.78
应用程序:ATM;SONET运营商类型:E-4
运营商类型(2):STS-3/OC-3数据速率:155520 Mbps
JESD-30 代码:S-PQFP-G52JESD-609代码:e0
长度:10 mm功能数量:1
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HQFP封装等效代码:QFP52,.47SQ
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified子类别:Digital Transmission Interfaces
最大压摆率:240 mA标称供电电压:5 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH NETWORK INTERFACE
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

S3016A 数据手册

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S3015/S3016  
E4/STM-1/OC-3 ATM INTERFACE CIRCUITS  
trolled Oscillator (VCO), which generates the recov-  
ered clock. Frequency stability without incoming data  
is guaranteed by an alternate reference input  
(REFCKIN) to which the PLL locks when data is lost.  
S3016 RECEIVER FUNCTIONAL  
DESCRIPTION  
The S3016 receiver provides the first stage of digital  
processing of a receive SONET STS-3 or ITU-T E4 serial  
bit stream. A Coded Mark Inversion (CMI) decoder can  
be enabled for decoding STS-3 electrical and E4 signals.  
When the test clock enable (TSTCLKEN) input is set  
high, the clock recovery block is disabled. The refer-  
ence clock (REFCKIN) is used as the bit rate clock  
input in place of the recovered clock. This feature is  
used for functional testing of the device.  
Clock recovery is performed on the incoming  
scrambled NRZ or CMI–coded data stream. A reference  
clock is required for phase locked loop start-up and  
proper operation under loss of signal conditions. An  
integral prescaler and phase locked loop circuit is used  
to multiply this reference frequency to the nominal bit rate.  
The loop filter transfer function is optimized to enable  
the PLL to track the jitter, yet tolerate the minimum  
transition density expected in a received SONET or  
E4 data signal. This transfer function yields a typical  
capture time of 16 µs for random incoming NRZ data.  
Clock Recovery  
The total loop dynamics of the clock recovery PLL yield  
a jitter tolerance which exceeds the minimum tolerance  
proposed for OC-3/STM-1/E4 equipment by the Bellcore  
and ITU-T documents, shown in Figure 13.  
The Clock Recovery function, as shown in the block  
diagram in Figure 10, generates a clock that is fre-  
quency matched to the incoming data baud rate at  
the SERDATIP/N differential inputs. The clock is  
phase aligned by a PLL so that it samples the data  
in the center of the data eye pattern.  
Optical and Electrical Interfaces  
The digital data inputs (SERDATIP/N) are the PECL  
inputs from an optical to electrical converter, as shown  
in Figure 16. The data input for the coaxial interface is  
ANDATIN, which is the serial data input from the equal-  
izer circuit and should be connected as shown in Figure  
17. The EQUALSEL input is used to select either  
SERDATIP/N or ANDATIN.  
The phase relationship between the edge transitions  
of the data and those of the generated clock are  
compared by a phase/frequency discriminator. Output  
pulses from the discriminator indicate the required  
direction of phase corrections. These pulses are  
smoothed by an integral loop filter. The output of the  
loop filter controls the frequency of the Voltage Con-  
Figure 10. S3016 OC-3/STM-1/E4 Receiver Functional Block Diagram  
CAP1  
LOOP  
VCO  
FILTER  
CAP2  
REFCKIN  
TSTCLKEN  
CMISEL  
REFCKOUT  
2
SERCLKOP/N  
LCV  
CLOCK  
DIVIDER  
C
M
I
LOCK  
LOSOUT  
DETECTOR  
RSTB  
2
BUFINA, BUFINB  
BUFOUT  
PHASE DETECTOR  
2
SERDATOP/N  
LOSOPT  
2:1  
MUX  
LOSIN  
LOSREF  
2
SERDATIP/N  
2:1  
MUX  
ANDATIN  
EQUALSEL  
6

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