Datasheet > S3017A/H1

S3017A/H1

更新时间： 2024-01-23 00:32:03

品牌	Logo	应用领域
AMCC		ATM 异步传输模式电信电信集成电路
页数	文件大小	规格书
22页	147K
描述
Transmitter, 1-Func, PQFP52, PLASTIC, QFP-52

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技术参数
数据手册

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S3017A/H1 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	52
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.81	应用程序：	ATM;SDH;SONET
JESD-30 代码：	S-PQFP-G52	长度：	10 mm
功能数量：	1	端子数量：	52
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	SQUARE	封装形式：	FLATPACK
认证状态：	Not Qualified	最大压摆率：	238 mA
标称供电电压：	5 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH TRANSMITTER	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	10 mm
Base Number Matches：	1

S3017A/H1 数据手册

DEVICE SPECIFICATION

SONET/SDH/ATM OC-12 TRANSMITTER AND RECEIVER

BiCMOS PECL CLOCK GENERATOR

S3017/S3018

S3017/S 018

SONET/SDH/ATM OC-12 TTRRAANNSSMMIITTTTEERRAANNDDRREECCEEIIVVEERR

FEATURES

GENERAL DESCRIPTION

The S3017/S3018 SONET/SDH/ATM transmitter and

receiver chips are fully integrated serialization/

deserializationSONETOC-12(622.08Mbit/s)interface

devices. With architecture developed by PMC-Sierra,

Inc., the chipset performs all necessary serial-to-paral-

lel and parallel-to-serial functions in conformance with

SONET/SDH transmission standards. The devices are

suitable for SONET-based ATM applications. Figure 1

shows a typical network application.

• Complies with ANSI, Bellcore, and ITU-T

specifications

• On-chip high-frequency PLL for clock

generation and clock recovery

• Supports 622.08 Mbit/s (OC-12/STM-4)

• Reference frequency of 77.76 MHz

• Interface to both PECL and TTL logic

• 8-bit TTL datapath

• Compact 52 PQFP TEP package

• Diagnostic loopback mode

• Lock detect

On-chip clock synthesis is performed by the high-

frequency phase-locked loop on the S3017 transmitter

chip allowing the use of a slower external transmit clock

reference. Clock recovery is performed on the S3018

receiver chip by synchronizing its on-chip VCO directly

to the incoming data stream. The S3018 also performs

SONET/SDH frame detection. The chipset can be used

with a 19.44 or 77.76 MHz reference clock, in support of

existing system clocking schemes.

• Low jitter PECL interface

• < 2.0 Watt per set typically

APPLICATIONS

• SONET/SDH-based transmission systems

• SONET/SDH modules

• SONET/SDH test equipment

• ATM over SONET/SDH

• Section repeaters

• Add drop multiplexors

• Broad-band cross-connects

• Fiber optic terminators

The low jitter PECL interface guarantees compliance

with the bit-error rate requirements of the Bellcore,

ANSI, and ITU-T standards. The S3017 and S3018 are

packaged in a compact 52 PQFP, offering designers a

small package outline.

• Fiber optic test equipment

Figure 1. System Block Diagram

S3017

S3018

SONET/

SDH/ATM

Receiver

Network

Interface

Processor

Network

Interface

Processor

SONET/

SDH/ATM

Transmitter

OTX

ORX

December 10, 1999 / Revision B

12 3 4 5 6 7...22

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与S3017A/H1相关器件

型号	品牌	描述	获取价格	数据表
S3017A/H2	AMCC	Transmitter, 1-Func, PQFP52, PLASTIC, QFP-52	获取价格
S3017C/H1	AMCC	Transmitter, 1-Func,	获取价格
S3017C/H2	AMCC	Transmitter, 1-Func,	获取价格
S3017-O	ETC	DESOLDERING BRAID	获取价格
S3018A	AMCC	ATM/SONET/SDH Receiver, PQFP52,	获取价格
S3018A/H1	AMCC	Receiver, 1-Func, PQFP52, PLASTIC, QFP-52	获取价格

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