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S2091A PDF预览

S2091A

更新时间: 2024-11-01 20:01:19
品牌 Logo 应用领域
AMCC 电信光电二极管电信集成电路
页数 文件大小 规格书
9页 108K
描述
Telecom Circuit, 1-Func, Bipolar, PDSO20, 4.40 X 6.50 MM, 0.90 MM HEIGHT, TSSOP-20

S2091A 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.24JESD-30 代码:R-PDSO-G20
长度:6.5 mm功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Other Telecom ICs
最大压摆率:230 mA标称供电电压:3.3 V
表面贴装:YES技术:BIPOLAR
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

S2091A 数据手册

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®
DEVICE  
SPECIFICATION  
S2091  
2.5 GBIT PORT BYPASS CIRCUIT FOR FIBRE CHANNEL ARBITRATED LOOP  
functional and data bypasses to the next available disk  
drive. Normal mode is enabled with a High on the SEL  
pin and Bypass mode is enable by a Low on the SEL  
pin. Direct Attach Fibre Channel Disk Drives have an  
“LRC Interlock” signal defined to control the SEL func-  
tion. A system diagram showing the S2091 in a single  
loop of a disk array is illustrated in Figure 2.  
FEATURES  
• Supports 2.5 Gbps Data Rates  
• Fully differential for minimum  
jitter accumulation  
• TTL Bypass Select  
• High speed 50source terminated outputs  
• 0.4W Typical power dissipation  
• 3.3V power supply  
The S2091 can be cascaded with the S3040 (Data  
retimer) for arrays of disk drives greater than 4.  
Table 1 is a truth table detailing the data flow  
through the S2091. Figure 3 shows a timing diagram  
of the data relationship in the S2091. The primary  
AC parameter of importance is the deterministic jitter  
or data eye degradation inserted by the port bypass  
circuit. The design for the S2091 minimized jitter ac-  
cumulation by using high bandwidth, low skew fully  
differential circuits. This provides for symmetric rise  
and fall delays as well as noise rejection.  
• 20 Pin TSSOP  
GENERAL DESCRIPTION  
The S2091 is a Port Bypass Circuit (PBC). A single  
channel Fibre Channel PBC offers designers maxi-  
mum flexibility in FC-AL disk architectures. The  
S2091 is designed to minimize jitter accumulation by  
providing a high bandwidth fully differential signal  
path. Port Bypass circuits are used to provide resil-  
iency in Fibre Channel Arbitrated Loop (FC-AL) ar-  
chitectures. PBC’s are used within FC-AL disk arrays  
to allow for resiliency and hot swapping of FC-AL  
drives.  
Table 1. Truth Table  
SEL1  
OUT  
IN  
DDO  
IN  
A Port-by-Pass Circuit is a 2:1 Multiplexer with two  
modes of operations: Normal and Bypass. In Normal  
mode, the disk drive is connected to the loop. In  
Bypass mode, the disk drive is either absent or non-  
0
1
DDI  
IN  
Figure 1. S2091 Block Diagram  
DDO P/N  
DDI P/N  
SEL  
1
0
IN P/N  
OUT P/N  
PBC  
1

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