Datasheet > S2092TT

S2092TT

更新时间： 2024-11-24 20:08:03

品牌	Logo	应用领域
AMCC		电信电信集成电路
页数	文件大小	规格书
15页	132K
描述
Telecom Circuit, 1-Func, PQFP48, 7 X 7 MM, HEAT SINK, TQFP-48

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中文翻译

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技术参数
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S2092TT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	HLFQFP,	针数：	48
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.82	JESD-30 代码：	S-PQFP-G48
长度：	7 mm	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HLFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.6 mm	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	7 mm	Base Number Matches：	1

S2092TT 数据手册

DEVICE

SPECIFICATION

SERIAL BACKPLANE RETIMER DEVICE

S2092

BiCMOS PECL CLOCK GENERATOR

SERIAL BACKPLANE RETIMER DEVICE

FEATURES

GENERAL DESCRIPTION

The function of the S2092 retimer device is to derive

high speed timing signals for DWDM equipment. The

S2092 is implemented using AMCC’s proven Phase

Lock Loop (PLL) technology. Figure 1 shows a typical

network application.

•

On-chip high frequency PLL with internal

loop filter for clock recovery

Internal 100 Ω line-to-line termination on

high speed differential input

Supports data recovery from:

The S2092 can receive a 2.488 Gbps to 2.67 Gbps

scrambled NRZ signal. This range is dependent on

the user's FEC needs and reference frequency selec-

tion. The S2092 recovers the clock from the data

and outputs the retimed data.

2.488 to 2.67 Gbps (2.488 Gbps with FEC

overhead data rate capability)

•

Selectable reference frequencies

Lock detect—monitors frequency of

incoming data

The S2092 utilizes an on-chip PLL which consists

of a phase detector, a loop filter, and a Voltage

Controlled Oscillator (VCO). The phase detector

compares the phase relationship between the VCO

output and the serial data input. A loop filter con-

verts the phase detector output into a smooth DC

voltage, and the DC voltage is input to the VCO

whose frequency is varied by this voltage. A block

diagram is shown in Figure 2.

•

Low-jitter serial CML interface

Single +3.3 V supply, 455 mW power

dissipation (typ)

•

Compact 7 mm x 7 mm 48 pin TQFP/TEP

package

APPLICATIONS

•

Dense Wavelength Division Multiplexing

(DWDM) systems

•

Serial Backplane interfaces

2.488 Gbps to 2.67 Gbps Short Haul

Retiming

•

Crosspoint interfaces

Figure 1. System Block Diagram

Port Card

S3056

S3057

Port Card

S3052

S3056

S3057

S3052

S3057

Switch Card

S2018

S2092

S3057

S2092

S3056

S3057

S3056

S3057

S3052

S3057

Port Card

July 10, 2000 / Revision A

12 3 4 5 6 7...15

中文翻译

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与S2092TT相关器件

型号	品牌	获取价格	描述	数据表
S2095PB	AMCC	获取价格	Telecom Circuit, 1-Func, CMOS, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
S2095PB11	AMCC	获取价格	Telecom Circuit, 1-Func, CMOS, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
S2095PB20	AMCC	获取价格	Telecom Circuit, 1-Func, CMOS, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
S2096PB20	AMCC	获取价格	Telecom Circuit, 1-Func, CMOS, PBGA256, 17 X 17 MM, PLASTIC, BGA-256
S209R	MINMAX	获取价格	2W, Low Cost DIP, Single & Dual Output DC/DC Converters
S20A1870N1	ANAREN	获取价格	Directional Coupler, 1750MHz Min, 1990MHz Max, 0.25dB Insertion Loss-Max, SURFACE MOUNT PA
S20A2500W1	ANAREN	获取价格	Directional Coupler, 2000MHz Min, 3000MHz Max, 0.25dB Insertion Loss-Max, SURFACE MOUNT PA
S20A-5SDAC	BOURNS	获取价格	DC-DC Regulated Power Supply Module, 1 Output, Hybrid, SIP-27
S20A-5SDAC-L	BOURNS	获取价格	DC-DC Regulated Power Supply Module, 1 Output, Hybrid, SIP-27
S20A-5SDAC-L2	BOURNS	获取价格	DC-DC Regulated Power Supply Module, 1 Output, Hybrid, SIP-27

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