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S2095PB20 PDF预览

S2095PB20

更新时间: 2024-11-01 20:07:27
品牌 Logo 应用领域
AMCC 电信电信集成电路
页数 文件大小 规格书
37页 270K
描述
Telecom Circuit, 1-Func, CMOS, PBGA256, 17 X 17 MM, PLASTIC, BGA-256

S2095PB20 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:256
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.65JESD-30 代码:S-PBGA-B256
长度:17 mm功能数量:1
端子数量:256最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:3.09 mm标称供电电压:1.8 V
表面贴装:YES技术:CMOS
电信集成电路类型:TELECOM CIRCUIT温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:17 mm
Base Number Matches:1

S2095PB20 数据手册

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Part Number S2095  
Revision NC - September 23, 2002  
DEVICE SPECIFICATION  
S2095  
1.86624 Gbps 12 Channel Receive Device  
FEATURES  
GENERAL DESCRIPTION  
0.18 µm CMOS Technology  
Operating rate  
- 1.86624 Gbps CML serial inputs  
- 933.12 Mbps LVDS parallel outputs  
The S2095 receives high-speed serial data in a variety  
of applications including terabit routers, serial back-  
planes, and proprietary point-to-point links. The chip  
provides two 11-bit parallel buses with associated  
clocks.  
Programmable register functions:  
- REFCLK frequency selection  
- PLL bypass operation  
Each channel provides serial-to-parallel data conver-  
sion and clock and data phase alignment. The on-chip  
receive Phase Lock Loop (PLL) is used to recover a  
clock and, in turn, feeds this clock into 12 channels.  
Each channel consists of an adjustable delay line and  
a phase detect circuit. The phase detect circuit deter-  
mines where the data transitions with respect to the  
falling edge of the clock. The decision circuitry is used  
to adjust the delay line according to the phase detec-  
tor’s response. Once the data is latched using the  
serial clock, the data is demuxed and written into the  
respective channel’s FIFO. The receiver supports dif-  
ferential CML compatible inputs for copper or fiber  
optic Physical Media Dependent (PMD) interfaces with  
excellent signal integrity. The chip requires a +1.8 V  
power supply and dissipates 3.6 W.  
- PLL loop bandwidth select  
Single PLL provides clock recovery  
Twelve independent low jitter Delay Lines and  
Phase Detector units provide phase alignment  
of data and clock  
High signal integrity line side data inputs  
- Internal 100 line to line terminations  
2.5 V tolerant CMOS inputs  
Single +1.8 V power supply  
3.6 W power dissipation (typ)  
Compact 17 mm x 17 mm 256-pin FCPBGA  
package  
APPLICATIONS  
Figure 1 shows the S2095 and S2096 (1.86624 Gbps  
12 Channel Transmit Device) in a Parallel Optical  
Interface application. Figure 2 shows the S2095 and  
S2096 with 12 channel transmit and receive optical  
modules to demonstrate a terabit router application  
using a parallel fiber interface. Figure 3 is the input/  
output diagram. Figure 4 shows the receive block  
diagram.  
Digital Crossconnect applications  
Serial Backplane system interfaces  
Parallel Fiber interfaces  
Terabit Router applications  
Optical Backplanes  
Figure 1. System Overview  
Parallel Optical Fiber  
12  
Channel  
Transmit  
Optical  
11  
11  
MAC  
(ASIC)  
S2096  
Module  
12 CHANNEL  
PARALLEL FIBER  
OPTICAL INTERFACE  
12  
11  
Channel  
Receive  
Optical  
Module  
MAC  
(ASIC)  
S2095  
11  
Parallel Optical Fiber  
AMCC Confidential and Proprietary  
1

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