Datasheet > S2096PB20

S2096PB20

更新时间： 2024-11-01 19:27:19

品牌	Logo	应用领域
AMCC		电信电信集成电路
页数	文件大小	规格书
34页	254K
描述
Telecom Circuit, 1-Func, CMOS, PBGA256, 17 X 17 MM, PLASTIC, BGA-256

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S2096PB20 技术参数

生命周期：	Transferred	零件包装代码：	BGA
包装说明：	BGA,	针数：	256
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.7	JESD-30 代码：	S-PBGA-B256
长度：	17 mm	功能数量：	1
端子数量：	256	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	认证状态：	Not Qualified
座面最大高度：	3.09 mm	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	宽度：	17 mm
Base Number Matches：	1

S2096PB20 数据手册

Confidential & Proprietary

Part Number S2096

PRELIMINARY MATERIAL

Revision A – September 23, 2002

Device Specification

S2096

1.86624 Gbps 12 Channel Transmit Device

FEATURES

APPLICATIONS

•

0.18 µm CMOS Technology

Operating rate

High-speed data communications

•

Digital Crossconnect applications

- 933.12 Mbps LVDS parallel inputs

- 1.86624 Gbps CML serial outputs

Serial Backplane system interfaces

Parallel Fiber interfaces

•

Programmable register functions:

- PLL bypass operation

- PLL loop bandwidth select

Transmitter PLL

- 2:1 multiplexing

- Low jitter on-chip clock synthesizer

Terabit Router applications

Optical backplanes

GENERAL DESCRIPTION

The S2096 facilitates high-speed serial transmission

of data in a variety of applications including terabit

routers, serial backplanes, and proprietary point-to-

point links. The chip provides two separate transmit-

ters, which are operated individually.

High signal integrity line side data outputs

- Low jitter, high symmetry, Current Mode

Logic (CML) data outputs

- 50 Ω output impedance (single ended)

2.5 V tolerant CMOS inputs

Each channel provides parallel-to-serial data conver-

sion. The on-chip transmit Phase Locked Loop (PLL)

synthesizes the high-speed clock from a low-speed

reference. The transmitter supports differential CML

compatible outputs for copper or fiber optic Physical

Media Dependent (PMD) interfaces with excellent sig-

nal integrity. The chip requires a +1.8 V power supply

and dissipates 3.2 W.

•

Interfaces with coax, twinax, or fiber optics

Single +1.8 V power supply

3.2 W power dissipation (typ)

Compact 17 mm x 17 mm 256-pin FC-PBGA

package

Figure 1 shows the S2096 and S2095 (1.86624 Gbps

12 Channel Receive Device) in a Parallel Optical Inter-

face application. Figure 2 shows the S2096 and S2095

with 12 channel transmit and receive optical modules

to demonstrate a terabit router application using a par-

allel fiber interface. Figure 3 is the input/output

diagram. Figure 4 shows the transmit block diagram.

Figure 1. System Overview

Parallel Optical Fiber

Channel

Transmit

Optical

MAC

S2096

(ASIC)

Channel

Parallel

Fiber

Module

Optical

Interface

Channel

Receive

Optical

MAC

(ASIC)

S2095

Module

Parallel Optical Fiber

This product is not released and the pinout and specification

herein are subject to change.

AMCC Confidential and Proprietary

DS0168

12 3 4 5 6 7...34

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