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S2068TB PDF预览

S2068TB

更新时间: 2024-11-01 21:20:55
品牌 Logo 应用领域
AMCC 以太网:16GBASE-T电信电信集成电路
页数 文件大小 规格书
24页 277K
描述
Ethernet Transceiver, 2-Trnsvr, Bipolar, PBGA156, 21 X 21 MM, COMPACT, TBGA-156

S2068TB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:21 X 21 MM, COMPACT, TBGA-156
针数:156Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.79
数据速率:1250000 MbpsJESD-30 代码:S-PBGA-B156
JESD-609代码:e0长度:21 mm
湿度敏感等级:4功能数量:2
端子数量:156收发器数量:2
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA156,16X16,50封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.65 mm子类别:Network Interfaces
最大压摆率:533 mA标称供电电压:3.3 V
表面贴装:YES技术:BIPOLAR
电信集成电路类型:ETHERNET TRANSCEIVER温度等级:COMMERCIAL
端子面层:TIN LEAD SILVER端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:21 mm
Base Number Matches:1

S2068TB 数据手册

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®
DEVICE  
SPECIFICATION  
S2068  
DUAL GIGABIT ETHERNET TRANSCEIVER  
FEATURES  
GENERAL DESCRIPTION  
• Functionally compliant with IEEE 802.3z Gigabit  
Ethernet Applications  
The S2068 dual transmitter and receiver chip is de-  
signed to provide two channels of high-speed serial  
data transmission over fiber optic or copper interfaces  
conforming to the requirements of the IEEE 802.3z  
Gigabit Ethernet specification. The chip runs at  
1250.0 Mbps serial data rate with an associated  
10-bit parallel data word. The chip provides two sepa-  
rate receive PLLs which can be operated asynchro-  
nously at slightly different frequencies.  
• 1250 MHz (Gigabit Ethernet) operating rate  
– Half rate operation  
• Dual Transmitter incorporating phase-locked  
loop (PLL) clock synthesis from low speed  
reference  
• Dual Receiver PLL provides clock and data  
recovery  
Each bi-directional channel provides parallel to serial  
and serial-to-parallel conversion, clock generation  
and recovery, and framing. The on-chip transmit PLL  
synthesizes the high-speed clock from a low-speed  
reference. The on-chip dual receive PLL is used for  
clock recovery and data re-timing on the two inde-  
pendent data inputs. The transmitter and receiver  
each support differential PECL-compatible I/O for  
copper or fiber optic component interfaces and pro-  
vide excellent signal integrity. Local loopback mode  
allows for system diagnostics. The chip requires a  
3.3V power supply and dissipates 1.37 watts.  
• Internally series terminated TTL outputs  
• Low-jitter serial PECL interface  
• Local Loopback  
• Interfaces with coax, twinax, or fiber optics  
• Single +3.3V supply, 1.37W power dissipation  
• Compact 21mm x 21mm 156 TBGA package  
APPLICATIONS  
High-speed data communications  
• Ethernet Backbones  
Figure 1 shows the use of the S2062 and S2068 in a  
Gigabit Ethernet application. Figure 2 summarizes  
the input/output signals of the device. Figures 3 and  
4 show the transmit and receive block diagrams, re-  
spectively.  
• Multi-port Gigabit Ethernet Cards  
• Switched networks  
• Data broadcast environments  
Figure 1. Typical Dual Gigabit Ethernet Application  
GE INTERFACE  
SERIAL BP DRIVER  
TO SERIAL  
BACKPLANE  
MAC  
(ASIC)  
DUAL  
GIGABIT  
ETHERNET  
INTERFACE  
S2062  
S2068  
MAC  
(ASIC)  
1
October 13, 2000 / Revision D  

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