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S2068TBI001 PDF预览

S2068TBI001

更新时间: 2024-11-01 21:02:43
品牌 Logo 应用领域
AMCC 以太网:16GBASE-T电信电信集成电路
页数 文件大小 规格书
28页 297K
描述
Ethernet Transceiver, PBGA156, 21 X 21 MM, TBGA-156

S2068TBI001 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:21 X 21 MM, TBGA-156针数:156
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:8.45JESD-30 代码:S-PBGA-B156
功能数量:1端子数量:156
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:COMMERCIAL端子形式:BALL
端子位置:BOTTOMBase Number Matches:1

S2068TBI001 数据手册

 浏览型号S2068TBI001的Datasheet PDF文件第2页浏览型号S2068TBI001的Datasheet PDF文件第3页浏览型号S2068TBI001的Datasheet PDF文件第4页浏览型号S2068TBI001的Datasheet PDF文件第5页浏览型号S2068TBI001的Datasheet PDF文件第6页浏览型号S2068TBI001的Datasheet PDF文件第7页 
®
DEVICE  
SPECIFICATION  
S2068TB001/TBI001  
DUAL GIGABIT ETHERNET TRANSCEIVER  
FEATURES  
GENERAL DESCRIPTION  
• Functionally compliant with IEEE 802.3z Gigabit  
Ethernet Applications  
The S2068TB001/TBI001 dual transmitter and re-  
ceiver chip is designed to provide two channels of  
high-speed serial data transmission over fiber optic or  
copper interfaces conforming to the requirements of  
the IEEE 802.3z Gigabit Ethernet specification. The  
chip runs at 1250.0 Mbps serial data rate with an  
associated 10-bit parallel data word. The chip pro-  
vides two separate receive PLLs which can be oper-  
ated asynchronously at slightly different frequencies.  
• 1250 MHz (Gigabit Ethernet) operating rate  
– Half rate operation  
• Dual Transmitter incorporating Phase-Locked  
Loop (PLL) clock synthesis from low speed  
reference  
• Dual Receiver PLL provides clock and data  
recovery  
Each bi-directional channel provides parallel to serial  
and serial-to-parallel conversion, clock generation  
and recovery, and framing. The on-chip transmit PLL  
synthesizes the high-speed clock from a low-speed  
reference. The on-chip dual receive PLL is used for  
clock recovery and data re-timing on the two inde-  
pendent data inputs. The transmitter and receiver  
each support differential PECL-compatible I/O for  
copper or fiber optic component interfaces and pro-  
vide excellent signal integrity. Local loopback mode  
allows for system diagnostics. The chip requires a  
3.3V power supply and dissipates 1.37 watts.  
• Internally series terminated TTL outputs  
• Low-jitter serial PECL interface  
• Local Loopback  
• Interfaces with coax, twinax, or fiber optics  
• Single +3.3V supply, 1.37W power dissipation  
• Compact 21mm x 21mm 156 TBGA package  
APPLICATIONS  
High-speed data communications  
• Ethernet Backbones  
Figure 1 shows the use of the S2062 and  
S2068TB001/TBI001 in a Gigabit Ethernet applica-  
tion. Figure 2 summarizes the input/output signals of  
the device. Figures 3 and 4 show the transmit and  
receive block diagrams, respectively.  
• Multi-port Gigabit Ethernet Cards  
• Switched networks  
• Data broadcast environments  
Figure 1. Typical Dual Gigabit Ethernet Application  
GE INTERFACE  
SERIAL BP DRIVER  
TO SERIAL  
BACKPLANE  
MAC  
(ASIC)  
DUAL  
GIGABIT  
ETHERNET  
INTERFACE  
S2068TB001/  
S2068TBI001  
S2062  
MAC  
(ASIC)  
1
November 19, 1999 / Revision NC  

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