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S2070A PDF预览

S2070A

更新时间: 2024-11-01 13:13:07
品牌 Logo 应用领域
AMCC 光纤以太网以太网:16GBASE-T
页数 文件大小 规格书
20页 168K
描述
Ethernet Transceiver, Bipolar, PQFP64, 10 X 10 MM, HEAT SPREADER, PLASTIC, QFP-64

S2070A 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP, QFP64,.51SQ,20针数:64
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.74Is Samacsys:N
JESD-30 代码:S-PQFP-G64长度:10 mm
功能数量:1端子数量:64
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP64,.51SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH电源:3.3 V
认证状态:Not Qualified座面最大高度:2.45 mm
子类别:Other Telecom ICs最大压摆率:235 mA
标称供电电压:3.3 V表面贴装:YES
技术:BIPOLAR电信集成电路类型:ETHERNET TRANSCEIVER
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

S2070A 数据手册

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®
DEVICE  
SPECIFICATION  
S2070  
FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER  
GENERAL DESCRIPTION  
FEATURES  
• 1062 Mbps (Fibre Channel) line rates  
• 1250 Mbps (Gigabit Ethernet) line rates  
• Half and full VCO output rates  
The S2070 transmitter and receiver chip facilitates  
high speed serial transmission of data over fiber op-  
tic, coax, or twinax interfaces. The device conforms  
to the requirements of the IEEE 802.3z Gigabit  
Ethernet Specification and the ANSI X3T11 Fibre  
Channel specification, and runs at 1062 Mbps or  
1250 Mbps data rates with an associated 10-bit data  
word.  
• Functionally compliant to IEEE 802.3z Gigabit  
Ethernet Specification and the ANSI X3T11  
Fibre Channel Specification  
• Transmitter incorporating phase-locked loop  
(PLL) clock synthesis from low speed reference  
The chip provides parallel-to-serial and serial-to-par-  
allel conversion, clock generation/recovery, and  
framing for block encoded data. The on-chip transmit  
PLL synthesizes the high-speed clock from a low-  
speed reference. The on-chip receive PLL performs  
clock recovery and data re-timing on the serial bit  
stream. The transmitter and receiver each support  
differential LVPECL compatible I/O for copper or fi-  
ber optic component interfaces with excellent signal  
integrity. Local loopback mode allows for system di-  
agnostics. The chip requires a +3.3 V power supply  
and dissipates approximately 620 mW under typical  
conditions.  
• Receiver PLL provides clock and data recovery  
• 10-bit parallel TTL compatible interface  
• Low-jitter serial LVPECL compatible interface  
• Local loopback  
• Single +3.3 V supply, 620 mW power dissipation  
• 64 PQFP package  
• Continuous downstream clocking from receiver  
• Drives 30 m of Twinax cable directly  
APPLICATIONS  
• Workstation  
The S2070 can be used for a variety of applications  
including Fibre Channel, serial backplanes, and pro-  
prietary point-to-point links. Figure 1 shows a typical  
configuration incorporating the chip.  
• Frame buffer  
• Switched networks  
• Data broadcast environments  
• Proprietary extended backplanes  
Figure 1. System Block Diagram  
Optical  
Gigabit  
Gigabit  
Ethernet/  
Fibre  
Optical  
Tx  
Rx  
Ethernet/  
S2070  
S2070  
Fibre  
Channel  
Controller  
Channel  
Controller  
Optical  
Rx  
Optical  
Tx  
1
March 7, 2001 / Revision G  

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