Datasheet > S2058A

S2058A

更新时间： 2024-11-01 20:57:23

品牌	Logo	应用领域
AMCC		电信光电二极管电信集成电路
页数	文件大小	规格书
11页	136K
描述
SPECIALTY TELECOM CIRCUIT, PDSO28, SOIC-28

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S2058A 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP28,.4	针数：	28
Reach Compliance Code：	unknown	风险等级：	5.7
JESD-30 代码：	R-PDSO-G28	长度：	17.8816 mm
功能数量：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP28,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	2.6416 mm
子类别：	Other Telecom ICs	标称供电电压：	3.3 V
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.4676 mm	Base Number Matches：	1

S2058A 数据手册

DEVICE

SPECIFICATION

PORT BYPASS AND REPEATER FOR FIBRE CHANNEL ARBITRATED LOOP

S2058

PORT BYPASS AND REPEATER FOR FIBRE CHANNEL ARBITRATED LOOP

detect circuit monitors the incoming signals for valid

8B/10B run length, transition density and frequency.

The output of this circuit is useful for link perfor-

mance monitoring and detection of channel present.

FEATURES

•

ANSI X3T11 Fibre Channel Compatible

Monolithic Clock Recovery Unit

– Re-times & Buffers Received Data

– Jitter Peaking < 0.15 dB

Jitter Performance

The S2058 complies with the minimum jitter toler-

ance requirements proposed by the Fibre Channel

jitter working group when used with differential in-

puts and outputs as shown in Figure 2. In addition,

the S2058 is designed for minimum jitter generation

and jitter transfer specifications. This allows the opti-

mum system design for arbitrated loop architectures.

•

Lock Detect Function

– Run Length Violation Detector

– Frequency Detection

•

Port Bypass Circuit

Suitable for both Coaxial and Optical Link

APPLICATIONS

Jitter Tolerance

•

Low Power Operation 0.425W, Typical

Input jitter tolerance is defined as the amplitude of

frequency dependent, random and deterministic jitter

that causes the clock recovery PLL to violate the

BER specifications. Input jitter tolerance specifica-

tions are shown in Figures 3 and 4.

106.25 or 53.125 MHz Reference Clock

28-Pin SOIC Package

3.3V Supply

GENERAL DESCRIPTION

The Fibre Channel Port Bypass with Repeater Cir-

cuit is used in full-speed (1.0625 Gb/s) Disk Arrays.

The S2058 block diagram is shown in Figure 1. It

contains a monolithic Clock Recovery Unit (CRU), a

lock detect feature and a port bypass Circuit. The

CRU may be used alone to implement a general

purpose Repeater needed for many Disk Array and

Switch applications where a re-timed and buffered

signal is required. The S2058 may be used to imple-

ment a single chip Arbitrated Loop Port Bypass Re-

timing Node. The S2058 performs the function of a

port bypass circuit followed by a clock and data

retiming Phase Locked Loop (CDR). The CDR re-

times incoming serial data, detects whether a valid

signal is present and outputs a low jitter serial data

stream.

Figure 1. S2058 Block Diagram

2.2 µF (X7R Type)

24Ω

OUT P/N

24Ω

LPF2

LPF1

REFSEL

LCKREFN

REFCLK

CDR

LOCKDET

TEST

normal

SEL

0 1

DDI P/N

FUNCTIONAL DESCRIPTION

The S2058 performs two functions. The first is a Port

Bypass Circuit (PBC) for nodes in a FC-AL system.

The low jitter accumulation of the Port Bypass Path

is essential in these systems. The second function is

to retime and restore signal quality in RAID drives

using the FC-AL link configuration. The low jitter

transfer peaking and the high jitter tolerance specifi-

cations of the Clock and Data Recovery PLL are

essential in these applications. In addition, the Lock

DDO P/N

S2058

IN P/N

12 3 4 5 6 7...11

中文翻译

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与S2058A相关器件

型号	品牌	获取价格	描述	数据表
S-2058-A	AMCC	获取价格	Telecom Circuit, 1-Func, PDSO28, SOIC-28
S2-05E	CYNERGY3	获取价格	Axial style reed relay
S2-05EU	CYNERGY3	获取价格	UL Approved Axial Style Reed Relay
S2-05P	CYNERGY3	获取价格	Axial style reed relay
S2-05PU	CYNERGY3	获取价格	UL Approved Axial Style Reed Relay
S205R	MINMAX	获取价格	2W, Low Cost DIP, Single & Dual Output DC/DC Converters
S2060	AMCC	获取价格	GPON Transceiver With CDR
S2060	MICROSEMI	获取价格	Silicon Power Rectifier
S2060-16.384	PERICOM	获取价格	CMOS Output Clock Oscillator, 16.384MHz Nom
S2060A	AMCC	获取价格	GIGABIT ETHERNET TRANSCEIVER

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