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S2066A PDF预览

S2066A

更新时间: 2024-11-01 20:09:07
品牌 Logo 应用领域
AMCC 以太网:16GBASE-T电信电信集成电路
页数 文件大小 规格书
28页 301K
描述
Ethernet Transceiver, 4-Trnsvr, Bipolar, PBGA208, 23 X 23 MM, COMPACT, TBGA-208

S2066A 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:23 X 23 MM, COMPACT, TBGA-208针数:208
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.79数据速率:1250000 Mbps
JESD-30 代码:S-PBGA-B208长度:23 mm
功能数量:4端子数量:208
收发器数量:4最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA208,17X17,50
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.65 mm子类别:Network Interfaces
最大压摆率:895 mA标称供电电压:3.3 V
表面贴装:YES技术:BIPOLAR
电信集成电路类型:ETHERNET TRANSCEIVER温度等级:COMMERCIAL
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:23 mm
Base Number Matches:1

S2066A 数据手册

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®
DEVICE  
SPECIFICATION  
S2066  
QUAD GIGABIT ETHERNET TRANSCEIVER  
FEATURES  
• Functionally compliant with IEEE 802.3z Gigabit  
Ethernet Applications  
GENERAL DESCRIPTION  
The S2066 quad transmitter and receiver chip is de-  
signed to provide four channels of high-speed serial  
data transmission over fiber optic or copper interfaces  
conforming to the requirements of the IEEE 802.3z  
Gigabit Ethernet specification. The chip runs at  
1250.0 Mbit/s serial data rate with an associated 10-  
bit parallel data word. The chip provides four separate  
transceivers which can be operated individually at  
slightly different frequencies.  
• 1250 MHz (Gigabit Ethernet) operating rate  
- 1/2 Rate Operation  
• Quad Transmitter incorporating phase-locked  
loop (PLL) clock synthesis from low speed  
reference  
• Quad Receiver PLL provides clock and data  
recovery  
• Internally series terminated TTL outputs  
• Low-jitter serial PECL interface  
Each bi-directional channel provides parallel to serial  
and serial to parallel conversion, clock generation  
and recovery, and framing. The on-chip transmit PLL  
synthesizes the high-speed clock from a low-speed  
reference. The on-chip quad receive PLL is used for  
clock recovery and data re-timing on the four inde-  
pendent data inputs. The transmitter and receiver  
each support differential PECL-compatible I/O for  
copper or fiber optic component interfaces and pro-  
vide excellent signal integrity. Local loopback mode  
allows for system diagnostics. The chip requires a  
3.3V power supply and dissipates approximately 2.3  
watts.  
• Local Loopback  
• Interfaces with coax, twinax, or fiber optics  
• Single +3.3V supply, 2.3 W Power dissipation  
• Compact 23mm x 23mm 208 TBGA package  
APPLICATIONS  
High-speed data communications  
• Ethernet Backbones  
• Multi-port Gigabit Ethernet Cards  
• Switched networks  
• Data broadcast environments  
Figure 1 shows the use of the S2064 and S2066 in a  
Gigabit Ethernet application. Figure 2 summarizes the  
input/output signals of the device. Figures 3 and 4  
show the transmit and receive block diagrams, re-  
spectively.  
Figure 1. Typical Quad Gigabit Ethernet Application  
GE INTERFACE  
SERIAL BP DRIVER  
MAC  
(ASIC)  
MAC  
(ASIC)  
TO SERIAL BACKPLANE  
QUAD  
S2064  
GIGABIT  
ETHERNET  
INTERFACE  
S2066  
MAC  
(ASIC)  
MAC  
(ASIC)  
1
October 13, 2000 / Revision C  

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