Datasheet > S2062TB

S2062TB

更新时间： 2024-11-01 21:09:59

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		/
页数	文件大小	规格书
27页	295K
描述
Ethernet Transceiver, PBGA156, 21 X 21 MM, COMPACT, TBGA-156

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中文翻译

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技术参数
数据手册

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S2062TB 技术参数

生命周期：	Contact Manufacturer	包装说明：	LBGA,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.81	Base Number Matches：	1

S2062TB 数据手册

DEVICE

SPECIFICATION

DUAL SERIAL BACKPLANE DEVICE

S2062

DUAL SERIAL BACKPLANE DEVICE

FEATURES

GENERAL DESCRIPTION

• Broad operating rate range (0.77 - 1.3 GHz)

- 1062 MHz (Fibre Channel)

The S2062 facilitates high-speed serial transmission

of data in a variety of applications including Gigabit

Ethernet, Fibre Channel, serial backplanes, and pro-

prietary point to point links. The chip provides two

separate transceivers which can be operated indi-

vidually for a data capacity of >2 Gbps.

- 1250 MHz (Gigabit Ethernet) line rates

- 1/2 Rate Operation

• Dual Transmitter with phase-locked loop (PLL)

clock synthesis from low speed reference

Each bi-directional channel provides 8B/10B coding/

decoding, parallel to serial and serial to parallel con-

version, clock generation/recovery, and framing. The

on-chip transmit PLL synthesizes the high-speed

clock from a low-speed reference. The on-chip dual

receive PLL is used for clock recovery and data re-

timing on the two independent data inputs. The

transmitter and receiver each support differential

PECL-compatible I/O for copper or fiber optic com-

ponent interfaces with excellent signal integrity. Lo-

cal loopback mode allows for system diagnostics.

The chip requires a 3.3V power supply and dissi-

pates 1.37 watts.

• Dual Receiver PLL provides clock and data

recovery

• Internally series terminated TTL outputs

• On-chip 8B/10B line encoding and decoding for

two separate parallel 8-bit channels

• 2x8 Bit parallel TTL interface

• Low-jitter serial PECL interface

• Local Loopback

• Interfaces with coax, twinax, or fiber optics

• Single +3.3V supply, 1.37 W power dissipation

• Compact 21mm x 21mm 156 TBGA package

Figure 1 shows the S2062 and S2068 in a Gigabit

Ethernet application. Figure 2 combines the

S2062 with a crosspoint switch to demonstrate a

serial backplane application. Figure 3 is the input/

output diagram. Figures 4 and 5 show the transmit

and receive block diagrams, respectively.

APPLICATIONS

• Ethernet Backbones

• Workstation

• Frame buffer

• Switched networks

• Data broadcast environments

• Proprietary extended backplanes

Figure 1. Typical Dual Gigabit Ethernet Application

GE INTERFACE

SERIAL BP DRIVER

TO SERIAL BACKPLANE

DUAL

GIGABIT

MAC

(ASIC)

ETHERNET

INTERFACE

S2068

S2062

MAC

(ASIC)

October 13, 2000 / Revision C

12 3 4 5 6 7...27

中文翻译

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与S2062TB相关器件

型号	品牌	获取价格	描述	数据表
S2063-FREQ-OUT25	DIODES	获取价格	ACMOS Output Clock Oscillator, 36MHz Min, 125MHz Max,
S2064A	AMCC	获取价格	Ethernet Transceiver, Bipolar, PBGA208, 23 X 23 MM, COMPACT, TBGA-208
S2065J	TECCOR	获取价格	SCRs 1-70 AMPS NON-SENSITIVE GATE
S2065J	LITTELFUSE	获取价格	SCRs (1 A to 70 A)
S2065J81	TECCOR	获取价格	Silicon Controlled Rectifier, 65A I(T)RMS, 200V V(DRM), 200V V(RRM), 1 Element, TO-218X, 3
S2065JTP	LITTELFUSE	获取价格	SCR NON-SENS 200V 65A ISO TO218X
S2065K	TECCOR	获取价格	SCRs
S2065K	LITTELFUSE	获取价格	SCRs (1 A to 70 A)
S2065K81	TECCOR	获取价格	Silicon Controlled Rectifier, 65A I(T)RMS, 200V V(DRM), 200V V(RRM), 1 Element, TO-218AC,
S2065KTP	LITTELFUSE	获取价格	SCR NON-SENS 200V 65A ISO TO-218

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