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S2060C

更新时间： 2024-11-01 06:09:43

品牌	Logo	应用领域
AMCC		以太网以太网：16GBASE-T
页数	文件大小	规格书
22页	696K
描述
GIGABIT ETHERNET TRANSCEIVER

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技术参数
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S2060C 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP, QFP64,.47SQ,20	针数：	64
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.75	数据速率：	1250000 Mbps
JESD-30 代码：	S-PQFP-G64	长度：	10 mm
功能数量：	1	端子数量：	64
收发器数量：	1	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP64,.47SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Network Interfaces
最大压摆率：	235 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
电信集成电路类型：	ETHERNET TRANSCEIVER	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	10 mm
Base Number Matches：	1

S2060C 数据手册

DEVICE

SPECIFICATION

GIGABIT ETHERNET TRANSCEIVER

S2060

GIGABIT ETHERNET TRANSCEIVER

GENERAL DESCRIPTION

FEATURES

• Operating rate

The S2060 transmitter and receiver chip facilitates

high speed serial transmission of data over fiber op-

tic, coax, or twinax interfaces. The device conforms

to the requirements of the IEEE 802.3z Gigabit

Ethernet specification, and runs at 1250.0 Mbps data

rates with an associated 10-bit data word.

• 1250 MHz (Gigabit Ethernet) line rates

• Half and full VCO output rates

• Functionally compliant IEEE 802.3z Gigabit

Ethernet standard

• Transmitter incorporating Phase-Locked Loop

(PLL) clock synthesis from low speed reference

The chip provides parallel-to-serial and serial-to-par-

allel conversion, clock generation/recovery, and

framing for block encoded data. The on-chip transmit

PLL synthesizes the high-speed clock from a low-

speed reference. The on-chip receive PLL performs

clock recovery and data re-timing on the serial bit

stream. The transmitter and receiver each support

differential LVPECL compatible I/O for copper or fi-

ber optic component interfaces with excellent signal

integrity. Local loopback mode allows for system di-

agnostics. The chip requires a +3.3 V power supply

and dissipates typically 620 mW.

• Receiver PLL provides clock and data recovery

• 10-bit parallel TTL compatible interface

• Low-jitter serial LVPECL compatible interface

• Local loopback

• Single +3.3 V supply, 620 mW power dissipation

• 64 PQFP or TQFP package

• Continuous downstream clocking from receiver

• Drives 30 m of Twinax cable directly

APPLICATIONS

The S2060 can be used for a variety of applications

including Gigabit Ethernet, serial backplanes, and

proprietary point-to-point links. Figure 1 shows a

typical configuration incorporating the chip.

• Workstation

• Frame buffer

• Switched networks

• Data broadcast environments

• Proprietary extended backplanes

Figure 1. System Block Diagram

Optical

Gigabit

Ethernet

Controller

Gigabit

Ethernet

Controller

S2060

Optical

March 7, 2001 / Revision H

12 3 4 5 6 7...22

中文翻译

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与S2060C相关器件

型号	品牌	获取价格	描述	数据表
S2060D	AMCC	获取价格	GIGABIT ETHERNET TRANSCEIVER
S2061B	ROCHESTER	获取价格	Ethernet Transceiver, PQFP64, 14 X 14 MM, HEAT SINK, PLASTIC, QFP-64
S2061B	AMCC	获取价格	Ethernet Transceiver, Bipolar, PQFP64, 14 X 14 MM, HEAT SINK, PLASTIC, QFP-64
S2062TB	AMCC	获取价格	Ethernet Transceiver, Bipolar, PBGA156, 21 X 21 MM, COMPACT, TBGA-156
S2062TB	ROCHESTER	获取价格	Ethernet Transceiver, PBGA156, 21 X 21 MM, COMPACT, TBGA-156
S2063-FREQ-OUT25	DIODES	获取价格	ACMOS Output Clock Oscillator, 36MHz Min, 125MHz Max,
S2064A	AMCC	获取价格	Ethernet Transceiver, Bipolar, PBGA208, 23 X 23 MM, COMPACT, TBGA-208
S2065J	TECCOR	获取价格	SCRs 1-70 AMPS NON-SENSITIVE GATE
S2065J	LITTELFUSE	获取价格	SCRs (1 A to 70 A)
S2065J81	TECCOR	获取价格	Silicon Controlled Rectifier, 65A I(T)RMS, 200V V(DRM), 200V V(RRM), 1 Element, TO-218X, 3

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