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S2044B-5 PDF预览

S2044B-5

更新时间: 2024-11-06 21:06:27
品牌 Logo 应用领域
AMCC 电信电信集成电路
页数 文件大小 规格书
20页 165K
描述
Telecom Circuit, 1-Func, PQFP52, 10 X 10 MM, PLASTIC, QFP-52

S2044B-5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP, QFP52,.52SQ
针数:52Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.73
JESD-30 代码:S-PQFP-G52JESD-609代码:e0
长度:10 mm功能数量:1
端子数量:52最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP52,.52SQ
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
认证状态:Not Qualified座面最大高度:2.45 mm
子类别:Other Telecom ICs最大压摆率:160 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

S2044B-5 数据手册

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®
PRELIMINARY  
DEVICE SPECIFICATION  
S2044/S2045  
GLM COMPLIANT SERIAL INTERFACE CIRCUITS  
FEATURES  
GENERAL DESCRIPTION  
• Complies with the electrical and link levels of  
the Gigabaud Link Module (GLM) specification  
• Functionally compliant with ANSI X3T11 Fibre  
Channel physical and transmission protocol  
standards  
• S2044 transmitter incorporates phase-locked  
loop (PLL) providing clock synthesis from low-  
speed reference  
The S2044 and S2045 transmitter and receiver pair  
are designed to perform high-speed serial data trans-  
mission over fiber optic or coaxial cable interfaces  
conforming to the requirements of the ANSI X3T11  
Fibre Channel specification. The chipset is Gigabaud  
Link Module (GLM) compliant and supports 1062 Mb/s  
(GLM) and 531 Mb/s Half-GLM (HGLM) and 266 Mb/s  
Quarter-GLM (QGLM) modes with associated 10 or  
20-bit data word.  
• S2045 receiver PLL configured for clock and  
data recovery  
The chipset performs parallel-to-serial and serial-to-  
parallel conversion and framing for block-encoded  
data. The S2044 on-chip PLL synthesizes the high-  
speed clock from a low-speed reference. The S2045  
on-chip PLL synchronizes directly to incoming digital  
signals, to receive the data stream. The transmitter  
and receiver each support differential PECL-compat-  
ible I/O for fiber optic component interfaces, to  
minimize crosstalk and maximize data integrity. Local  
loopback allows for system diagnostics. The I/O sec-  
tion can operate from either a +3.3V or a +5V power  
supply. With a 3.3V power supply the chipset dissi-  
pates only 1W typically.  
• 1062 Mb/s (GLM), 531 Mb/s (HGLM) and  
266 Mb/s (QGLM) operation  
• 10- or 20-bit parallel TTL compatible interface  
• 1 watt typical power dissipation for chipset  
• +3.3/+5V power supply  
• Low-jitter serial PECL compatible interface  
• Lock detect  
• Local loopback  
• Compact 52 PQFP package  
• Fibre Channel framing performed by receiver  
• Continuous downstream clocking from receiver  
• TTL compatible outputs possible with +5V I/O  
power supply  
Figure 1 shows a typical network configuration incor-  
porating the chipset. The chipset is compatible with  
AMCC’s S2036 Open Fiber Control (OFC) device.  
APPLICATIONS  
High-speed data communications  
• Mainframe/Workstation  
• Switched networks  
• Proprietary extended backplanes  
• Mass storage devices/RAID drives  
Figure 1. System Block Diagram  
S2036  
Open  
Fiber  
Control  
(OFC)  
Optical  
S2045  
RX  
RX  
S2044  
TX  
Optical  
TX  
Fibre  
Channel  
Controller  
Fibre  
Channel  
Controller  
S2044  
Optical  
S2045  
RX  
Optical  
RX  
TX  
TX  
S2036  
Open  
Fiber  
Control  
(OFC)  
1

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