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S2047B-5/D PDF预览

S2047B-5/D

更新时间: 2024-11-06 19:59:11
品牌 Logo 应用领域
AMCC 电信电信集成电路
页数 文件大小 规格书
23页 165K
描述
Interface Circuit, PQFP52, 10 X 10 MM, COMPACT, PLASTIC, QFP-52

S2047B-5/D 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:52
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.83JESD-30 代码:S-PQFP-G52
长度:10 mm功能数量:1
端子数量:52最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
座面最大高度:2.45 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:INTERFACE CIRCUIT
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

S2047B-5/D 数据手册

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®
DEVICE SPECIFICATION  
S2046/S2047  
GIGABIT ETHERNET CHIPSET  
FEATURES  
GENERAL DESCRIPTION  
• Functionally compliant with the IEEE 802.3z  
Specification  
• S2046 transmitter incorporates phase-locked  
loop (PLL) providing clock synthesis from low-  
speed reference  
• S2047 receiver PLL configured for clock and  
data recovery  
• 1250 Mb/s (Gigabit Ethernet) operation  
• 10-bit or 20-bit parallel TTL compatible  
interface  
The S2046 and S2047 transmitter and receiver pair  
are designed to perform high-speed serial data trans-  
mission over fiber optic or coaxial cable interfaces  
conforming to the requirements of the IEEE 802.3z  
specification. The chipset is Gigabit Ethernet compli-  
ant and supports 1250 Mb/s with an associated 10 or  
20-bit data word.  
The chipset performs parallel-to-serial and serial-to-  
parallel conversion and framing for block-encoded  
data. The S2046 on-chip PLL synthesizes the high-  
speed clock from a low-speed reference. The S2047  
on-chip PLL synchronizes directly to incoming digital  
signals, to receive the data stream. The transmitter  
and receiver each support differential PECL-compat-  
ible I/O for fiber optic component interfaces, to  
minimize crosstalk and maximize data integrity. Local  
loopback allows for system diagnostics. The I/O sec-  
tion can operate from either a +3.3 V or a +5 V power  
supply. With a 3.3 V power supply the chipset dissi-  
pates only 1 W typically.  
• 1 watt typical power dissipation for chipset  
• +3.3/+5 V power supply  
• Low-jitter serial PECL compatible interface  
• Lock detect  
• Local loopback  
• Compact 52 pin PQFP package  
• Fibre Channel framing performed by receiver  
• Continuous downstream clocking from receiver  
• TTL compatible outputs possible with +5V I/O  
power supply  
APPLICATIONS  
High-speed data communications  
• Ethernet backbone connections  
• Mainframe  
Figure 1 shows a typical network configuration incor-  
porating the chipset.  
• Workstation  
• Frame buffer  
• Switched networks  
• Data broadcast environments  
• Proprietary extended backplanes  
Figure 1. System Block Diagram  
Optical  
S2047  
RX  
RX  
S2046  
TX  
Optical  
TX  
Gigabit  
Ethernet  
Controller  
Gigabit  
Ethernet  
Controller  
S2046  
Optical  
S2047  
RX  
Optical  
RX  
TX  
TX  
May 16, 2000 / Revision NC  
1

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